forked from OSchip/llvm-project
[VE] half fptrunc+store&load+fpext
Summary: fp16 (half) load+fpext and fptrunc+store isel legalization and tests. Also, ExternalSymbolSDNode operand printing (tested by fp16 lowering). Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73899
This commit is contained in:
Kazushi (Jam) Marukawa
Simon Moll
parent
e943329ba0
commit
3ed12232b0
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@ -523,10 +523,14 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
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addRegisterClass(MVT::f64, &VE::I64RegClass);
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/// Load & Store {
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// Turn FP extload into load/fpextend
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for (MVT VT : MVT::fp_valuetypes()) {
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
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for (MVT FPVT : MVT::fp_valuetypes()) {
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for (MVT OtherFPVT : MVT::fp_valuetypes()) {
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// Turn FP extload into load/fpextend
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setLoadExtAction(ISD::EXTLOAD, FPVT, OtherFPVT, Expand);
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// Turn FP truncstore into trunc + store.
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setTruncStoreAction(FPVT, OtherFPVT, Expand);
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}
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}
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// VE doesn't have i1 sign extending load
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@ -536,9 +540,6 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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setTruncStoreAction(VT, MVT::i1, Expand);
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}
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// Turn FP truncstore into trunc + store.
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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/// } Load & Store
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// Custom legalize address nodes into LO/HI parts.
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@ -563,12 +564,20 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::UDIVREM, IntVT, Expand);
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}
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/// Conversion {
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// VE doesn't have instructions for fp<->uint, so expand them by llvm
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); // use i64
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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// fp16 not supported
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for (MVT FPVT : MVT::fp_valuetypes()) {
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setOperationAction(ISD::FP16_TO_FP, FPVT, Expand);
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setOperationAction(ISD::FP_TO_FP16, FPVT, Expand);
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}
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/// } Conversion
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setStackPointerRegisterToSaveRestore(VE::SX11);
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// Set function alignment to 16 bytes
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@ -612,6 +621,10 @@ SDValue VETargetLowering::withTargetFlags(SDValue Op, unsigned TF,
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return DAG.getTargetBlockAddress(BA->getBlockAddress(), Op.getValueType(),
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0, TF);
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if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
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return DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0),
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TF);
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llvm_unreachable("Unhandled address SDNode");
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}
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@ -1129,6 +1129,13 @@ def : Pat<(add (VEhi tglobaladdr:$in1), (VElo tglobaladdr:$in2)),
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(LEASLrzi (ANDrm0 (LEAzzi tglobaladdr:$in2), 32),
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(tglobaladdr:$in1))>;
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// Address calculation and its optimization
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def : Pat<(VEhi texternalsym:$in), (LEASLzzi texternalsym:$in)>;
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def : Pat<(VElo texternalsym:$in), (ANDrm0 (LEAzzi texternalsym:$in), 32)>;
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def : Pat<(add (VEhi texternalsym:$in1), (VElo texternalsym:$in2)),
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(LEASLrzi (ANDrm0 (LEAzzi texternalsym:$in2), 32),
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(texternalsym:$in1))>;
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// Calls
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def : Pat<(call tglobaladdr:$dst),
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(CALL tglobaladdr:$dst)>;
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@ -46,6 +46,9 @@ static MCOperand LowerOperand(const MachineInstr *MI, const MachineOperand &MO,
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break;
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return MCOperand::createReg(MO.getReg());
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case MachineOperand::MO_ExternalSymbol:
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return LowerSymbolOperand(
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MI, MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
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case MachineOperand::MO_GlobalAddress:
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return LowerSymbolOperand(MI, MO, AP.getSymbol(MO.getGlobal()), AP);
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case MachineOperand::MO_Immediate:
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@ -1,5 +1,113 @@
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; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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declare i16 @llvm.convert.to.fp16.f32(float %a)
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declare i16 @llvm.convert.to.fp16.f64(double %a)
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declare float @llvm.convert.from.fp16.f32(i16 %a)
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declare double @llvm.convert.from.fp16.f64(i16 %a)
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define float @func_i16fp32(i16* %a) {
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; CHECK-LABEL: func_i16fp32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: ld2b.zx %s0, (,%s0)
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; CHECK-NEXT: lea %s1, __gnu_h2f_ieee@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(%s1)
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; CHECK-NEXT: bsic %lr, (,%s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%a.val = load i16, i16* %a, align 4
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%a.asd = call float @llvm.convert.from.fp16.f32(i16 %a.val)
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ret float %a.asd
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}
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define double @func_i16fp64(i16* %a) {
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; CHECK-LABEL: func_i16fp64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: ld2b.zx %s0, (,%s0)
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; CHECK-NEXT: lea %s1, __gnu_h2f_ieee@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(%s1)
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; CHECK-NEXT: bsic %lr, (,%s12)
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; CHECK-NEXT: cvt.d.s %s0, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%a.val = load i16, i16* %a, align 4
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%a.asd = call double @llvm.convert.from.fp16.f64(i16 %a.val)
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ret double %a.asd
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}
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define float @func_fp16fp32(half* %a) {
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; CHECK-LABEL: func_fp16fp32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: ld2b.zx %s0, (,%s0)
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; CHECK-NEXT: lea %s1, __gnu_h2f_ieee@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(%s1)
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; CHECK-NEXT: bsic %lr, (,%s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%a.val = load half, half* %a, align 4
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%a.asd = fpext half %a.val to float
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ret float %a.asd
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}
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define double @func_fp16fp64(half* %a) {
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; CHECK-LABEL: func_fp16fp64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: ld2b.zx %s0, (,%s0)
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; CHECK-NEXT: lea %s1, __gnu_h2f_ieee@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(%s1)
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; CHECK-NEXT: bsic %lr, (,%s12)
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; CHECK-NEXT: cvt.d.s %s0, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%a.val = load half, half* %a, align 4
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%a.asd = fpext half %a.val to double
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ret double %a.asd
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}
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define void @func_fp32i16(i16* %fl.ptr, float %val) {
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; CHECK-LABEL: func_fp32i16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: st %s18, 48(,%s9) # 8-byte Folded Spill
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; CHECK-NEXT: or %s18, 0, %s0
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; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __gnu_f2h_ieee@hi(%s0)
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: bsic %lr, (,%s12)
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; CHECK-NEXT: st2b %s0, (,%s18)
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; CHECK-NEXT: ld %s18, 48(,%s9) # 8-byte Folded Reload
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; CHECK-NEXT: or %s11, 0, %s9
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%val.asf = call i16 @llvm.convert.to.fp16.f32(float %val)
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store i16 %val.asf, i16* %fl.ptr
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ret void
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}
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define half @func_fp32fp16(half* %fl.ptr, float %a) {
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; CHECK-LABEL: func_fp32fp16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: st %s18, 48(,%s9) # 8-byte Folded Spill
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; CHECK-NEXT: st %s19, 56(,%s9) # 8-byte Folded Spill
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; CHECK-NEXT: or %s18, 0, %s0
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; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __gnu_f2h_ieee@hi(%s0)
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: bsic %lr, (,%s12)
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; CHECK-NEXT: or %s19, 0, %s0
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; CHECK-NEXT: lea %s0, __gnu_h2f_ieee@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(%s0)
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; CHECK-NEXT: or %s0, 0, %s19
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; CHECK-NEXT: bsic %lr, (,%s12)
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; CHECK-NEXT: st2b %s19, (,%s18)
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; CHECK-NEXT: ld %s19, 56(,%s9) # 8-byte Folded Reload
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; CHECK-NEXT: ld %s18, 48(,%s9) # 8-byte Folded Reload
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; CHECK-NEXT: or %s11, 0, %s9
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%a.asd = fptrunc float %a to half
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store half %a.asd, half* %fl.ptr
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ret half %a.asd
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}
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define double @func_fp32fp64(float* %a) {
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; CHECK-LABEL: func_fp32fp64:
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; CHECK: .LBB{{[0-9]+}}_2:
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@ -11,6 +119,42 @@ define double @func_fp32fp64(float* %a) {
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ret double %a.asd
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}
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define void @func_fp64i16(i16* %fl.ptr, double %val) {
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; CHECK-LABEL: func_fp64i16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: st %s18, 48(,%s9) # 8-byte Folded Spill
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; CHECK-NEXT: or %s18, 0, %s0
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; CHECK-NEXT: lea %s0, __truncdfhf2@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __truncdfhf2@hi(%s0)
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: bsic %lr, (,%s12)
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; CHECK-NEXT: st2b %s0, (,%s18)
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; CHECK-NEXT: ld %s18, 48(,%s9) # 8-byte Folded Reload
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; CHECK-NEXT: or %s11, 0, %s9
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%val.asf = call i16 @llvm.convert.to.fp16.f64(double %val)
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store i16 %val.asf, i16* %fl.ptr
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ret void
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}
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define void @func_fp64fp16(half* %fl.ptr, double %val) {
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; CHECK-LABEL: func_fp64fp16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: st %s18, 48(,%s9) # 8-byte Folded Spill
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; CHECK-NEXT: or %s18, 0, %s0
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; CHECK-NEXT: lea %s0, __truncdfhf2@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __truncdfhf2@hi(%s0)
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: bsic %lr, (,%s12)
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; CHECK-NEXT: st2b %s0, (,%s18)
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; CHECK-NEXT: ld %s18, 48(,%s9) # 8-byte Folded Reload
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; CHECK-NEXT: or %s11, 0, %s9
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%val.asf = fptrunc double %val to half
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store half %val.asf, half* %fl.ptr
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ret void
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}
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define void @func_fp64fp32(float* %fl.ptr, double %val) {
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; CHECK-LABEL: func_fp64fp32:
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; CHECK: .LBB{{[0-9]+}}_2:
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