forked from OSchip/llvm-project
[SLP]Unify vectorization of PHI and store nodes with improved tiny tree vectorization.
Vectorization of PHIs and stores very similar, it might be beneficial to try to revectorize stores (like PHIs) if the total number of stores with the same/alternate opcode is less than the vector size but number of stores with the same type is larger than the vector size. Differential Revision: https://reviews.llvm.org/D109831
This commit is contained in:
Alexey Bataev
parent
5f8228d310
commit
3ea7877c8b
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@ -8989,6 +8989,78 @@ bool SLPVectorizerPass::vectorizeSimpleInstructions(
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return OpsChanged;
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}
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template <typename T>
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static bool
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tryToVectorizeSequence(SmallVectorImpl<T *> &Incoming,
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function_ref<unsigned(T *)> Limit,
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function_ref<bool(T *, T *)> Comparator,
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function_ref<bool(T *, T *)> AreCompatible,
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function_ref<bool(ArrayRef<T *>, bool)> TryToVectorize,
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bool LimitForRegisterSize) {
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bool Changed = false;
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// Sort by type, parent, operands.
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stable_sort(Incoming, Comparator);
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// Try to vectorize elements base on their type.
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SmallVector<T *> Candidates;
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for (auto *IncIt = Incoming.begin(), *E = Incoming.end(); IncIt != E;) {
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// Look for the next elements with the same type, parent and operand
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// kinds.
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auto *SameTypeIt = IncIt;
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while (SameTypeIt != E && AreCompatible(*SameTypeIt, *IncIt))
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++SameTypeIt;
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// Try to vectorize them.
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unsigned NumElts = (SameTypeIt - IncIt);
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LLVM_DEBUG(dbgs() << "SLP: Trying to vectorize starting at nodes ("
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<< NumElts << ")\n");
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// The vectorization is a 3-state attempt:
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// 1. Try to vectorize instructions with the same/alternate opcodes with the
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// size of maximal register at first.
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// 2. Try to vectorize remaining instructions with the same type, if
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// possible. This may result in the better vectorization results rather than
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// if we try just to vectorize instructions with the same/alternate opcodes.
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// 3. Final attempt to try to vectorize all instructions with the
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// same/alternate ops only, this may result in some extra final
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// vectorization.
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if (NumElts > 1 &&
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TryToVectorize(makeArrayRef(IncIt, NumElts), LimitForRegisterSize)) {
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// Success start over because instructions might have been changed.
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Changed = true;
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} else if (NumElts < Limit(*IncIt) &&
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(Candidates.empty() ||
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Candidates.front()->getType() == (*IncIt)->getType())) {
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Candidates.append(IncIt, std::next(IncIt, NumElts));
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}
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// Final attempt to vectorize instructions with the same types.
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if (Candidates.size() > 1 &&
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(SameTypeIt == E || (*SameTypeIt)->getType() != (*IncIt)->getType())) {
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if (TryToVectorize(Candidates, /*LimitForRegisterSize=*/false)) {
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// Success start over because instructions might have been changed.
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Changed = true;
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} else if (LimitForRegisterSize) {
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// Try to vectorize using small vectors.
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for (auto *It = Candidates.begin(), *End = Candidates.end();
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It != End;) {
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auto *SameTypeIt = It;
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while (SameTypeIt != End && AreCompatible(*SameTypeIt, *It))
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++SameTypeIt;
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unsigned NumElts = (SameTypeIt - It);
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if (NumElts > 1 && TryToVectorize(makeArrayRef(It, NumElts),
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/*LimitForRegisterSize=*/false))
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Changed = true;
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It = SameTypeIt;
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}
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}
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Candidates.clear();
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}
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// Start over at the next instruction of a different type (or the end).
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IncIt = SameTypeIt;
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}
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return Changed;
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}
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bool SLPVectorizerPass::vectorizeChainsInBlock(BasicBlock *BB, BoUpSLP &R) {
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bool Changed = false;
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SmallVector<Value *, 4> Incoming;
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@ -8997,11 +9069,89 @@ bool SLPVectorizerPass::vectorizeChainsInBlock(BasicBlock *BB, BoUpSLP &R) {
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// node. Allows better to identify the chains that can be vectorized in the
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// better way.
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DenseMap<Value *, SmallVector<Value *, 4>> PHIToOpcodes;
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auto PHICompare = [this, &PHIToOpcodes](Value *V1, Value *V2) {
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assert(isValidElementType(V1->getType()) &&
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isValidElementType(V2->getType()) &&
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"Expected vectorizable types only.");
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// It is fine to compare type IDs here, since we expect only vectorizable
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// types, like ints, floats and pointers, we don't care about other type.
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if (V1->getType()->getTypeID() < V2->getType()->getTypeID())
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return true;
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if (V1->getType()->getTypeID() > V2->getType()->getTypeID())
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return false;
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ArrayRef<Value *> Opcodes1 = PHIToOpcodes[V1];
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ArrayRef<Value *> Opcodes2 = PHIToOpcodes[V2];
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if (Opcodes1.size() < Opcodes2.size())
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return true;
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if (Opcodes1.size() > Opcodes2.size())
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return false;
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for (int I = 0, E = Opcodes1.size(); I < E; ++I) {
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// Undefs are compatible with any other value.
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if (isa<UndefValue>(Opcodes1[I]) || isa<UndefValue>(Opcodes2[I]))
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continue;
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if (auto *I1 = dyn_cast<Instruction>(Opcodes1[I]))
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if (auto *I2 = dyn_cast<Instruction>(Opcodes2[I])) {
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DomTreeNodeBase<BasicBlock> *NodeI1 = DT->getNode(I1->getParent());
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DomTreeNodeBase<BasicBlock> *NodeI2 = DT->getNode(I2->getParent());
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if (!NodeI1)
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return NodeI2 != nullptr;
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if (!NodeI2)
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return false;
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assert((NodeI1 == NodeI2) ==
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(NodeI1->getDFSNumIn() == NodeI2->getDFSNumIn()) &&
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"Different nodes should have different DFS numbers");
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if (NodeI1 != NodeI2)
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return NodeI1->getDFSNumIn() < NodeI2->getDFSNumIn();
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InstructionsState S = getSameOpcode({I1, I2});
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if (S.getOpcode())
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continue;
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return I1->getOpcode() < I2->getOpcode();
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}
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if (isa<Constant>(Opcodes1[I]) && isa<Constant>(Opcodes2[I]))
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continue;
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if (Opcodes1[I]->getValueID() < Opcodes2[I]->getValueID())
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return true;
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if (Opcodes1[I]->getValueID() > Opcodes2[I]->getValueID())
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return false;
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}
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return false;
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};
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auto AreCompatiblePHIs = [&PHIToOpcodes](Value *V1, Value *V2) {
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if (V1 == V2)
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return true;
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if (V1->getType() != V2->getType())
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return false;
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ArrayRef<Value *> Opcodes1 = PHIToOpcodes[V1];
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ArrayRef<Value *> Opcodes2 = PHIToOpcodes[V2];
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if (Opcodes1.size() != Opcodes2.size())
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return false;
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for (int I = 0, E = Opcodes1.size(); I < E; ++I) {
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// Undefs are compatible with any other value.
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if (isa<UndefValue>(Opcodes1[I]) || isa<UndefValue>(Opcodes2[I]))
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continue;
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if (auto *I1 = dyn_cast<Instruction>(Opcodes1[I]))
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if (auto *I2 = dyn_cast<Instruction>(Opcodes2[I])) {
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if (I1->getParent() != I2->getParent())
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return false;
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InstructionsState S = getSameOpcode({I1, I2});
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if (S.getOpcode())
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continue;
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return false;
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}
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if (isa<Constant>(Opcodes1[I]) && isa<Constant>(Opcodes2[I]))
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continue;
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if (Opcodes1[I]->getValueID() != Opcodes2[I]->getValueID())
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return false;
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}
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return true;
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};
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auto Limit = [&R](Value *V) {
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unsigned EltSize = R.getVectorElementSize(V);
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return std::max(2U, R.getMaxVecRegSize() / EltSize);
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};
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bool HaveVectorizedPhiNodes = true;
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while (HaveVectorizedPhiNodes) {
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HaveVectorizedPhiNodes = false;
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bool HaveVectorizedPhiNodes = false;
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do {
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// Collect the incoming values from the PHIs.
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Incoming.clear();
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for (Instruction &I : *BB) {
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@ -9039,158 +9189,15 @@ bool SLPVectorizerPass::vectorizeChainsInBlock(BasicBlock *BB, BoUpSLP &R) {
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}
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}
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// Sort by type, parent, operands.
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stable_sort(Incoming, [this, &PHIToOpcodes](Value *V1, Value *V2) {
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assert(isValidElementType(V1->getType()) &&
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isValidElementType(V2->getType()) &&
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"Expected vectorizable types only.");
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// It is fine to compare type IDs here, since we expect only vectorizable
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// types, like ints, floats and pointers, we don't care about other type.
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if (V1->getType()->getTypeID() < V2->getType()->getTypeID())
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return true;
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if (V1->getType()->getTypeID() > V2->getType()->getTypeID())
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return false;
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ArrayRef<Value *> Opcodes1 = PHIToOpcodes[V1];
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ArrayRef<Value *> Opcodes2 = PHIToOpcodes[V2];
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if (Opcodes1.size() < Opcodes2.size())
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return true;
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if (Opcodes1.size() > Opcodes2.size())
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return false;
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for (int I = 0, E = Opcodes1.size(); I < E; ++I) {
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// Undefs are compatible with any other value.
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if (isa<UndefValue>(Opcodes1[I]) || isa<UndefValue>(Opcodes2[I]))
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continue;
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if (auto *I1 = dyn_cast<Instruction>(Opcodes1[I]))
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if (auto *I2 = dyn_cast<Instruction>(Opcodes2[I])) {
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DomTreeNodeBase<BasicBlock> *NodeI1 = DT->getNode(I1->getParent());
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DomTreeNodeBase<BasicBlock> *NodeI2 = DT->getNode(I2->getParent());
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if (!NodeI1)
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return NodeI2 != nullptr;
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if (!NodeI2)
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return false;
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assert((NodeI1 == NodeI2) ==
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(NodeI1->getDFSNumIn() == NodeI2->getDFSNumIn()) &&
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"Different nodes should have different DFS numbers");
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if (NodeI1 != NodeI2)
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return NodeI1->getDFSNumIn() < NodeI2->getDFSNumIn();
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InstructionsState S = getSameOpcode({I1, I2});
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if (S.getOpcode())
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continue;
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return I1->getOpcode() < I2->getOpcode();
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}
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if (isa<Constant>(Opcodes1[I]) && isa<Constant>(Opcodes2[I]))
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continue;
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if (Opcodes1[I]->getValueID() < Opcodes2[I]->getValueID())
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return true;
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if (Opcodes1[I]->getValueID() > Opcodes2[I]->getValueID())
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return false;
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}
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return false;
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});
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auto &&AreCompatiblePHIs = [&PHIToOpcodes](Value *V1, Value *V2) {
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if (V1 == V2)
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return true;
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if (V1->getType() != V2->getType())
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return false;
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ArrayRef<Value *> Opcodes1 = PHIToOpcodes[V1];
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ArrayRef<Value *> Opcodes2 = PHIToOpcodes[V2];
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if (Opcodes1.size() != Opcodes2.size())
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return false;
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for (int I = 0, E = Opcodes1.size(); I < E; ++I) {
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// Undefs are compatible with any other value.
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if (isa<UndefValue>(Opcodes1[I]) || isa<UndefValue>(Opcodes2[I]))
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continue;
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if (auto *I1 = dyn_cast<Instruction>(Opcodes1[I]))
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if (auto *I2 = dyn_cast<Instruction>(Opcodes2[I])) {
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if (I1->getParent() != I2->getParent())
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return false;
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InstructionsState S = getSameOpcode({I1, I2});
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if (S.getOpcode())
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continue;
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return false;
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}
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if (isa<Constant>(Opcodes1[I]) && isa<Constant>(Opcodes2[I]))
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continue;
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if (Opcodes1[I]->getValueID() != Opcodes2[I]->getValueID())
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return false;
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}
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return true;
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};
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// Try to vectorize elements base on their type.
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SmallVector<Value *, 4> Candidates;
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for (SmallVector<Value *, 4>::iterator IncIt = Incoming.begin(),
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E = Incoming.end();
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IncIt != E;) {
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// Look for the next elements with the same type, parent and operand
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// kinds.
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SmallVector<Value *, 4>::iterator SameTypeIt = IncIt;
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while (SameTypeIt != E && AreCompatiblePHIs(*SameTypeIt, *IncIt)) {
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VisitedInstrs.insert(*SameTypeIt);
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++SameTypeIt;
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}
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// Try to vectorize them.
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unsigned NumElts = (SameTypeIt - IncIt);
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LLVM_DEBUG(dbgs() << "SLP: Trying to vectorize starting at PHIs ("
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<< NumElts << ")\n");
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// The order in which the phi nodes appear in the program does not matter.
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// So allow tryToVectorizeList to reorder them if it is beneficial. This
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// is done when there are exactly two elements since tryToVectorizeList
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// asserts that there are only two values when AllowReorder is true.
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// The vectorization is a 3-state attempt:
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// 1. Try to vectorize PHIs with the same/alternate opcodes with the size
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// of maximal register at first.
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// 2. Try to vectorize remaining PHIs with the same type, if possible.
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// This may result in the better vectorization results rather than if we
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// try just to vectorize PHIs with the same/alternate opcodes.
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// 3. Final attempt to try to vectorize all PHIs with the same/alternate
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// ops only, this may result in some extra final vectorization.
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if (NumElts > 1 && tryToVectorizeList(makeArrayRef(IncIt, NumElts), R,
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/*LimitForRegisterSize=*/true)) {
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// Success start over because instructions might have been changed.
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HaveVectorizedPhiNodes = true;
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Changed = true;
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} else if (NumElts * R.getVectorElementSize(*IncIt) <
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R.getMaxVecRegSize() &&
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(Candidates.empty() ||
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Candidates.front()->getType() == (*IncIt)->getType())) {
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Candidates.append(IncIt, std::next(IncIt, NumElts));
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}
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// Final attempt to vectorize phis with the same types.
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if (Candidates.size() > 1 &&
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(SameTypeIt == E ||
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(*SameTypeIt)->getType() != (*IncIt)->getType())) {
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if (tryToVectorizeList(Candidates, R)) {
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// Success start over because instructions might have been changed.
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HaveVectorizedPhiNodes = true;
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Changed = true;
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} else {
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// Try to vectorize using small vectors.
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for (SmallVector<Value *, 4>::iterator It = Candidates.begin(),
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End = Candidates.end();
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It != End;) {
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SmallVector<Value *, 4>::iterator SameTypeIt = It;
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while (SameTypeIt != End && AreCompatiblePHIs(*SameTypeIt, *It))
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++SameTypeIt;
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unsigned NumElts = (SameTypeIt - It);
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if (NumElts > 1 &&
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tryToVectorizeList(makeArrayRef(It, NumElts), R)) {
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HaveVectorizedPhiNodes = true;
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Changed = true;
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}
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It = SameTypeIt;
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}
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}
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Candidates.clear();
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}
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// Start over at the next instruction of a different type (or the end).
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IncIt = SameTypeIt;
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}
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}
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HaveVectorizedPhiNodes = tryToVectorizeSequence<Value>(
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Incoming, Limit, PHICompare, AreCompatiblePHIs,
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[this, &R](ArrayRef<Value *> Candidates, bool LimitForRegisterSize) {
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return tryToVectorizeList(Candidates, R, LimitForRegisterSize);
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},
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/*LimitForRegisterSize=*/true);
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Changed |= HaveVectorizedPhiNodes;
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VisitedInstrs.insert(Incoming.begin(), Incoming.end());
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} while (HaveVectorizedPhiNodes);
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VisitedInstrs.clear();
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@ -9443,6 +9450,10 @@ bool SLPVectorizerPass::vectorizeStoreChains(BoUpSLP &R) {
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return V1->getValueOperand()->getValueID() ==
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V2->getValueOperand()->getValueID();
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};
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auto Limit = [&R, this](StoreInst *SI) {
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unsigned EltSize = DL->getTypeSizeInBits(SI->getValueOperand()->getType());
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return R.getMinVF(EltSize);
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};
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// Attempt to sort and vectorize each of the store-groups.
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for (auto &Pair : Stores) {
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@ -9452,33 +9463,15 @@ bool SLPVectorizerPass::vectorizeStoreChains(BoUpSLP &R) {
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LLVM_DEBUG(dbgs() << "SLP: Analyzing a store chain of length "
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<< Pair.second.size() << ".\n");
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stable_sort(Pair.second, StoreSorter);
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if (!isValidElementType(Pair.second.front()->getValueOperand()->getType()))
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continue;
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// Try to vectorize elements based on their compatibility.
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for (ArrayRef<StoreInst *>::iterator IncIt = Pair.second.begin(),
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E = Pair.second.end();
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IncIt != E;) {
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// Look for the next elements with the same type.
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ArrayRef<StoreInst *>::iterator SameTypeIt = IncIt;
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Type *EltTy = (*IncIt)->getPointerOperand()->getType();
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while (SameTypeIt != E && AreCompatibleStores(*SameTypeIt, *IncIt))
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++SameTypeIt;
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// Try to vectorize them.
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unsigned NumElts = (SameTypeIt - IncIt);
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LLVM_DEBUG(dbgs() << "SLP: Trying to vectorize starting at stores ("
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<< NumElts << ")\n");
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if (NumElts > 1 && !EltTy->getPointerElementType()->isVectorTy() &&
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vectorizeStores(makeArrayRef(IncIt, NumElts), R)) {
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// Success start over because instructions might have been changed.
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Changed = true;
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}
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// Start over at the next instruction of a different type (or the end).
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IncIt = SameTypeIt;
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}
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Changed |= tryToVectorizeSequence<StoreInst>(
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Pair.second, Limit, StoreSorter, AreCompatibleStores,
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[this, &R](ArrayRef<StoreInst *> Candidates, bool) {
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return vectorizeStores(Candidates, R);
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},
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/*LimitForRegisterSize=*/false);
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}
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return Changed;
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}
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@ -313,21 +313,18 @@ define void @tiny_vector_with_diff_opcode(i16 *%a, i16 *%v1) {
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; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* [[V1:%.*]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 undef to i16
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; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds i16, i16* [[A:%.*]], i64 0
|
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; CHECK-NEXT: store i16 [[TMP1]], i16* [[PTR0]], align 16
|
||||
; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 1
|
||||
; CHECK-NEXT: store i16 [[TMP2]], i16* [[PTR1]], align 4
|
||||
; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 2
|
||||
; CHECK-NEXT: store i16 [[TMP1]], i16* [[PTR2]], align 8
|
||||
; CHECK-NEXT: [[PTR3:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 3
|
||||
; CHECK-NEXT: store i16 [[TMP2]], i16* [[PTR3]], align 4
|
||||
; CHECK-NEXT: [[PTR4:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 4
|
||||
; CHECK-NEXT: store i16 [[TMP1]], i16* [[PTR4]], align 16
|
||||
; CHECK-NEXT: [[PTR5:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 5
|
||||
; CHECK-NEXT: store i16 [[TMP2]], i16* [[PTR5]], align 4
|
||||
; CHECK-NEXT: [[PTR6:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 6
|
||||
; CHECK-NEXT: store i16 [[TMP1]], i16* [[PTR6]], align 8
|
||||
; CHECK-NEXT: [[PTR7:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 7
|
||||
; CHECK-NEXT: store i16 [[TMP2]], i16* [[PTR7]], align 4
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> poison, i16 [[TMP1]], i32 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[TMP2]], i32 1
|
||||
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[TMP4]], <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16* [[PTR0]] to <8 x i16>*
|
||||
; CHECK-NEXT: store <8 x i16> [[SHUFFLE]], <8 x i16>* [[TMP5]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
%1 = load i16, i16* %v1, align 4
|
||||
|
|
|
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Loading…
Reference in New Issue