forked from OSchip/llvm-project
parent
6233189713
commit
3e6ee1db3e
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@ -98,16 +98,28 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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Value = (Hi4 << 16) | (Lo12);
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return Value;
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}
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case ARM::fixup_arm_ldst_pcrel_12: {
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bool isAdd = true;
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case ARM::fixup_arm_ldst_pcrel_12:
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// ARM PC-relative values are offset by 8.
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Value -= 8;
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Value -= 6;
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case ARM::fixup_t2_ldst_pcrel_12: {
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// Offset by 4, adjusted by two due to the half-word ordering of thumb.
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Value -= 2;
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bool isAdd = true;
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if ((int64_t)Value < 0) {
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Value = -Value;
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isAdd = false;
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}
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assert ((Value < 4096) && "Out of range pc-relative fixup value!");
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Value |= isAdd << 23;
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// Same addressing mode as fixup_arm_pcrel_10,
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// but with 16-bit halfwords swapped.
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if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
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uint64_t swapped = (Value & 0xFFFF0000) >> 16;
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swapped |= (Value & 0x0000FFFF) << 16;
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return swapped;
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}
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return Value;
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}
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case ARM::fixup_arm_adr_pcrel_12: {
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@ -128,7 +140,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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// Offset by 8 just as above.
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return 0xffffff & ((Value - 8) >> 2);
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case ARM::fixup_t2_branch: {
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Value = Value - 6;
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Value = Value - 8;
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Value >>= 1; // Low bit is not encoded.
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uint64_t out = 0;
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@ -310,6 +322,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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return 3;
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case FK_Data_4:
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case ARM::fixup_t2_ldst_pcrel_12:
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case ARM::fixup_t2_branch:
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case ARM::fixup_t2_pcrel_10:
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case ARM::fixup_arm_thumb_bl:
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@ -18,6 +18,11 @@ enum Fixups {
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// fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
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// addresses
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fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
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// fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
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// the 16-bit halfwords reordered.
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fixup_t2_ldst_pcrel_12,
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// fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
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// used in VFP instructions where the lower 2 bits are not encoded
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// (so it's encoded as an 8-bit immediate).
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@ -47,6 +47,7 @@ public:
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const static MCFixupKindInfo Infos[] = {
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// name off bits flags
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{ "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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@ -508,7 +509,12 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
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else
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Expr = MO2.getExpr();
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MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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MCFixupKind Kind;
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if (Subtarget.isThumb2())
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Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
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else
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Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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++MCNumCPRelocations;
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