forked from OSchip/llvm-project
Revert "Differential Revision: https://reviews.llvm.org/D99812"
This reverts commit c729f2a48a.
This commit is contained in:
Anshil Gandhi
parent
07a6beb402
commit
3e5ddb83e3
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@ -13,13 +13,7 @@
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//===----------------------------------------------------------------------===//
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#include "PPCCallLowering.h"
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#include "PPCISelLowering.h"
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#include "PPCSubtarget.h"
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#include "PPCTargetMachine.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/TargetCallingConv.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "ppc-call-lowering"
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@ -42,85 +36,18 @@ bool PPCCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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return true;
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}
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bool PPCCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const {
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return false;
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}
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bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const auto &DL = F.getParent()->getDataLayout();
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auto &TLI = *getTLI<PPCTargetLowering>();
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// Loop over each arg, set flags and split to single value types
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SmallVector<ArgInfo, 8> SplitArgs;
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unsigned I = 0;
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for (const auto &Arg : F.args()) {
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if (DL.getTypeStoreSize(Arg.getType()).isZero())
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continue;
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ArgInfo OrigArg{VRegs[I], Arg};
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setArgFlags(OrigArg, I + AttributeList::FirstArgIndex, DL, F);
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splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
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++I;
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}
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CCAssignFn *AssignFn =
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TLI.ccAssignFnForCall(F.getCallingConv(), false, F.isVarArg());
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IncomingValueAssigner ArgAssigner(AssignFn);
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FormalArgHandler ArgHandler(MIRBuilder, MRI);
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return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
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MIRBuilder, F.getCallingConv(),
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F.isVarArg());
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// If VRegs is empty, then there are no formal arguments to lower and thus can
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// always return true. If there are formal arguments, we currently do not
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// handle them and thus return false.
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return VRegs.empty();
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}
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void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
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Register PhysReg,
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CCValAssign &VA) {
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markPhysRegUsed(PhysReg);
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IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
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}
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void PPCIncomingValueHandler::assignValueToAddress(Register ValVReg,
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Register Addr, uint64_t Size,
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MachinePointerInfo &MPO,
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CCValAssign &VA) {
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assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
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"Unsupported size");
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// define a lambda expression to load value
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auto BuildLoad = [](MachineIRBuilder &MIRBuilder, MachinePointerInfo &MPO,
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uint64_t Size, const DstOp &Res, Register Addr) {
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MachineFunction &MF = MIRBuilder.getMF();
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auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size,
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inferAlignFromPtrInfo(MF, MPO));
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return MIRBuilder.buildLoad(Res, Addr, *MMO);
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};
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BuildLoad(MIRBuilder, MPO, Size, ValVReg, Addr);
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}
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Register PPCIncomingValueHandler::getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) {
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auto &MFI = MIRBuilder.getMF().getFrameInfo();
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const bool IsImmutable = !Flags.isByVal();
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int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
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MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
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// Build Frame Index based on whether the machine is 32-bit or 64-bit
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llvm::LLT FramePtr = LLT::pointer(
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0, MIRBuilder.getMF().getDataLayout().getPointerSizeInBits());
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MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI);
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StackUsed = std::max(StackUsed, Size + Offset);
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return AddrReg.getReg(0);
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}
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void FormalArgHandler::markPhysRegUsed(unsigned PhysReg) {
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MIRBuilder.getMRI()->addLiveIn(PhysReg);
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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bool PPCCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const {
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return false;
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}
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@ -35,38 +35,6 @@ public:
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bool lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const override;
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};
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class PPCIncomingValueHandler : public CallLowering::IncomingValueHandler {
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public:
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PPCIncomingValueHandler(MachineIRBuilder &MIRBuilder,
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MachineRegisterInfo &MRI)
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: CallLowering::IncomingValueHandler(MIRBuilder, MRI) {}
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uint64_t StackUsed;
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private:
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void assignValueToReg(Register ValVReg, Register PhysReg,
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CCValAssign &VA) override;
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void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
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MachinePointerInfo &MPO, CCValAssign &VA) override;
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Register getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) override;
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virtual void markPhysRegUsed(unsigned PhysReg) = 0;
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};
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class FormalArgHandler : public PPCIncomingValueHandler {
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void markPhysRegUsed(unsigned PhysReg) override;
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public:
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FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
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: PPCIncomingValueHandler(MIRBuilder, MRI) {}
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};
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} // end namespace llvm
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#endif
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@ -17360,14 +17360,3 @@ PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent,
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}
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return Mode;
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}
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CCAssignFn *PPCTargetLowering::ccAssignFnForCall(CallingConv::ID CC,
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bool Return,
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bool IsVarArg) const {
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switch (CC) {
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case CallingConv::Cold:
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return (Return ? RetCC_PPC_Cold : CC_PPC64_ELF_FIS);
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default:
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return CC_PPC64_ELF_FIS;
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}
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}
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@ -1116,9 +1116,6 @@ namespace llvm {
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HasNest(HasNest), NoMerge(NoMerge) {}
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};
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CCAssignFn *ccAssignFnForCall(CallingConv::ID CC, bool Return,
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bool IsVarArg) const;
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private:
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struct ReuseLoadInfo {
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SDValue Ptr;
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@ -1,181 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
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%struct.A = type { i8, float, i32, i32, i32 }
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define void @f() {
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; CHECK-LABEL: name: f
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo1(i32 %x){
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; CHECK-LABEL: name: foo1
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo2(i64 %x){
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; CHECK-LABEL: name: foo2
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo3(<7 x i8> %x) {
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; CHECK-LABEL: name: foo3
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
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; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64), [[COPY6]](s64)
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; CHECK: [[TRUNC7:%[0-9]+]]:_(<7 x s8>) = G_TRUNC [[BUILD_VECTOR]](<7 x s64>)
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo_notrunc(<7 x i64> %x) {
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; CHECK-LABEL: name: foo_notrunc
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
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; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64), [[COPY6]](s64)
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo_pt(<7 x i8>* %x) {
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; CHECK-LABEL: name: foo_pt
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x3
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define dso_local void @foo_struct(%struct.A %a) #0 {
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; CHECK-LABEL: name: foo_struct
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; CHECK: bb.1.entry:
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; CHECK: liveins: $f1, $x3, $x4, $x5, $x6
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $f1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x6
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; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
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; CHECK: BLR8 implicit $lr8, implicit $rm
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entry:
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ret void
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}
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define void @foo_int(i32* %x) {
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; CHECK-LABEL: name: foo_int
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x3
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo(float* %x) {
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; CHECK-LABEL: name: foo
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x3
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo_multiple(i1 %a, i8 %b, i16 %c, i32 %d, i64 %e, i128 %f){
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; CHECK-LABEL: name: foo_multiple
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64)
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s64)
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
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; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
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; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
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; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY5]](s64), [[COPY6]](s64)
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo_multiple_same_ty(i64 %x, i64 %y, i64 %z){
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; CHECK-LABEL: name: foo_multiple_same_ty
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3, $x4, $x5
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo_float(float %x) {
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; CHECK-LABEL: name: foo_float
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $f1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo_dbl(double %x) {
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; CHECK-LABEL: name: foo_dbl
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $f1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $f1
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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define void @foo_array([7 x i8] %x) {
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; CHECK-LABEL: name: foo_array
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64)
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s64)
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
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; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[COPY3]](s64)
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
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; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[COPY4]](s64)
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
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; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[COPY5]](s64)
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; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
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; CHECK: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[COPY6]](s64)
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; CHECK: BLR8 implicit $lr8, implicit $rm
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ret void
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}
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@ -0,0 +1,7 @@
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
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; CHECK: name: f
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; CHECK: BLR8
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define void @f() {
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ret void
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}
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