forked from OSchip/llvm-project
parent
72d195ecf0
commit
3e0b4b0eb7
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@ -17308,7 +17308,7 @@ static SDValue LowerZERO_EXTEND_Mask(SDValue Op,
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SDLoc DL(Op);
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unsigned NumElts = VT.getVectorNumElements();
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// For all vectors, but vXi8 we can just emit a sign_extend a shift. This
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// For all vectors, but vXi8 we can just emit a sign_extend and a shift. This
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// avoids a constant pool load.
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if (VT.getVectorElementType() != MVT::i8) {
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SDValue Extend = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, In);
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@ -19520,7 +19520,7 @@ static SDValue LowerSIGN_EXTEND_Mask(SDValue Op,
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unsigned NumElts = VT.getVectorNumElements();
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// Extend VT if the scalar type is v8/v16 and BWI is not supported.
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// Extend VT if the scalar type is i8/i16 and BWI is not supported.
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MVT ExtVT = VT;
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if (!Subtarget.hasBWI() && VTElt.getSizeInBits() <= 16) {
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// If v16i32 is to be avoided, we'll need to split and concatenate.
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