forked from OSchip/llvm-project
X86, AArch64, ARM: Do not attach debug location to spill/reload instructions
Spill/reload instructions are artificially generated by the compiler and have no relation to the original source code. So the best thing to do is not attach any debug location to them (instead of just taking the next debug location we find on following instructions). Differential Revision: https://reviews.llvm.org/D52125 llvm-svn: 343520
This commit is contained in:
Matthias Braun
parent
1346b5b7cf
commit
3e081703c3
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@ -2748,9 +2748,6 @@ void AArch64InstrInfo::storeRegToStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
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bool isKill, int FI, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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@ -2797,7 +2794,7 @@ void AArch64InstrInfo::storeRegToStackSlot(
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Opc = AArch64::ST1Twov1d;
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Offset = false;
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} else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, MBBI, DL, get(AArch64::STPXi))
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BuildMI(MBB, MBBI, DebugLoc(), get(AArch64::STPXi))
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.addReg(TRI->getSubReg(SrcReg, AArch64::sube64),
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getKillRegState(isKill))
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.addReg(TRI->getSubReg(SrcReg, AArch64::subo64),
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@ -2843,7 +2840,7 @@ void AArch64InstrInfo::storeRegToStackSlot(
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}
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assert(Opc && "Unknown register class");
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const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
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const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI);
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@ -2856,9 +2853,6 @@ void AArch64InstrInfo::loadRegFromStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
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int FI, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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@ -2905,7 +2899,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
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Opc = AArch64::LD1Twov1d;
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Offset = false;
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} else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, MBBI, DL, get(AArch64::LDPXi))
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BuildMI(MBB, MBBI, DebugLoc(), get(AArch64::LDPXi))
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.addReg(TRI->getSubReg(DestReg, AArch64::sube64),
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getDefRegState(true))
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.addReg(TRI->getSubReg(DestReg, AArch64::subo64),
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@ -2951,7 +2945,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
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}
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assert(Opc && "Unknown register class");
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const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
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const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
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.addReg(DestReg, getDefRegState(true))
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.addFrameIndex(FI);
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if (Offset)
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@ -971,8 +971,6 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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@ -984,7 +982,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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switch (TRI->getSpillSize(*RC)) {
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case 2:
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if (ARM::HPRRegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, I, DL, get(ARM::VSTRH))
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BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0)
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@ -995,14 +993,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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break;
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case 4:
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if (ARM::GPRRegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, I, DL, get(ARM::STRi12))
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BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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} else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, I, DL, get(ARM::VSTRS))
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BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0)
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@ -1013,7 +1011,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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break;
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case 8:
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if (ARM::DPRRegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, I, DL, get(ARM::VSTRD))
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BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0)
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@ -1021,7 +1019,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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.add(predOps(ARMCC::AL));
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} else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
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if (Subtarget.hasV5TEOps()) {
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
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MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
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AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
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AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
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MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
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@ -1029,7 +1027,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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} else {
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// Fallback to STM instruction, which has existed since the dawn of
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// time.
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STMIA))
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MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
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.addFrameIndex(FI)
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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@ -1043,14 +1041,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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if (ARM::DPairRegClass.hasSubClassEq(RC)) {
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// Use aligned spills if the stack can be realigned.
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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BuildMI(MBB, I, DL, get(ARM::VST1q64))
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BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
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.addFrameIndex(FI)
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.addImm(16)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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} else {
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BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
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BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addMemOperand(MMO)
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@ -1063,14 +1061,15 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
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// Use aligned spills if the stack can be realigned.
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
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BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
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.addFrameIndex(FI)
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.addImm(16)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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} else {
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
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MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
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get(ARM::VSTMDIA))
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.addFrameIndex(FI)
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.add(predOps(ARMCC::AL))
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.addMemOperand(MMO);
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@ -1086,14 +1085,15 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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// FIXME: It's possible to only store part of the QQ register if the
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// spilled def has a sub-register index.
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BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
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BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
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.addFrameIndex(FI)
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.addImm(16)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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} else {
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
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MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
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get(ARM::VSTMDIA))
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.addFrameIndex(FI)
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.add(predOps(ARMCC::AL))
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.addMemOperand(MMO);
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@ -1107,7 +1107,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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break;
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case 64:
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if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
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MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
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.addFrameIndex(FI)
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.add(predOps(ARMCC::AL))
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.addMemOperand(MMO);
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@ -3313,8 +3313,7 @@ void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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(Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
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RI.canRealignStack(MF);
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unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
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DebugLoc DL = MBB.findDebugLoc(MI);
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
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addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
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.addReg(SrcReg, getKillRegState(isKill));
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}
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@ -3348,8 +3347,7 @@ void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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(Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
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RI.canRealignStack(MF);
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unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
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DebugLoc DL = MBB.findDebugLoc(MI);
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
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addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
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}
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void X86InstrInfo::loadRegFromAddr(
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@ -0,0 +1,32 @@
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# RUN: llc -o - %s -run-pass=regallocfast | FileCheck %s
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--- |
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target triple = "aarch64--"
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!0 = !DIFile(filename: "test.ll", directory: "/")
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!1 = distinct !DICompileUnit(file: !0, language: DW_LANG_C)
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!2 = distinct !DISubprogram(name: "test")
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!3 = !DILocation(line: 17, scope: !2)
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!4 = !DILocation(line: 42, scope: !2)
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define void @func() {
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unreachable
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}
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...
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---
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# CHECK-LABEL: name: func
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name: func
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK: LDRXui killed $x0
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; Should find a spill here, but it should not have a debug-location.
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; CHECK-NOT: STRXui {{.*}}debug-location
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; CHECK: BLR
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; Should find a reload here, but it should not have a debug-location.
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; CHECK-NOT: LDRXui {{.*}}debug-location
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; CHECK: STRXui {{.*}}, killed $x0
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%0 : gpr64 = LDRXui $x0, 0, debug-location !3
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; an instruction with regmask should force us to spill %0
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BLR undef $x0, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $x0, debug-location !3
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STRXui %0, $x0, 0, debug-location !4
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@ -55,7 +55,7 @@
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; V5RNGLISTS-NOT: DW_TAG
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; V5RNGLISTS: DW_AT_rnglists_base [DW_FORM_sec_offset] (0x0000000c)
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; V5RNGLISTS: .debug_rnglists contents:
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; V5RNGLISTS-NEXT: 0x00000000: range list header: length = 0x00000014, version = 0x0005,
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; V5RNGLISTS-NEXT: 0x00000000: range list header: length = 0x00000015, version = 0x0005,
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; V5RNGLISTS-SAME: addr_size = 0x08, seg_size = 0x00, offset_entry_count = 0x00000000
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; V5RNGLISTS-NEXT: ranges:
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; V5RNGLISTS-NEXT: 0x0000000c: [DW_RLE_offset_pair]:
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@ -28,7 +28,8 @@
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; CHECK: DW_TAG_subprogram
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; CHECK: DW_AT_name{{.*}} = "func"
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; CHECK: DW_TAG_formal_parameter
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; CHECK: DW_AT_location {{.*}} (DW_OP_breg4 RSI+0, DW_OP_deref)
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; CHECK: DW_AT_location {{.*}}
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; CHECK-NEXT: DW_OP_breg4 RSI+0, DW_OP_deref
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; CHECK-NOT: DW_TAG
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; CHECK: DW_AT_name{{.*}} = "f"
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