forked from OSchip/llvm-project
AMDGPU/SI: Propagate the Kill flag in storeRegToStackSlot and eliminateFrameIndex
Reviewers: arsenm, tstellarAMD Differential Revision: http://reviews.llvm.org/21438 llvm-svn: 272958
This commit is contained in:
Changpeng Fang
parent
280ecf6ff0
commit
3e06e1edac
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@ -601,7 +601,7 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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// SGPRs.
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unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize());
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BuildMI(MBB, MI, DL, get(Opcode))
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.addReg(SrcReg) // src
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.addReg(SrcReg, getKillRegState(isKill)) // src
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.addFrameIndex(FrameIndex) // frame_idx
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.addMemOperand(MMO);
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@ -623,7 +623,7 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize());
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MFI->setHasSpilledVGPRs();
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BuildMI(MBB, MI, DL, get(Opcode))
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.addReg(SrcReg) // src
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.addReg(SrcReg, getKillRegState(isKill)) // src
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.addFrameIndex(FrameIndex) // frame_idx
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.addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
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.addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
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@ -399,12 +399,14 @@ static unsigned getNumSubRegsForSpillOp(unsigned Op) {
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void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
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unsigned LoadStoreOp,
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unsigned Value,
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const MachineOperand *SrcDst,
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unsigned ScratchRsrcReg,
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unsigned ScratchOffset,
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int64_t Offset,
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RegScavenger *RS) const {
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unsigned Value = SrcDst->getReg();
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bool IsKill = SrcDst->isKill();
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction *MF = MI->getParent()->getParent();
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const SIInstrInfo *TII =
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@ -453,8 +455,12 @@ void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
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Value;
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unsigned SOffsetRegState = 0;
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if (i + 1 == e && Scavenged)
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SOffsetRegState |= RegState::Kill;
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unsigned SrcDstRegState = getDefRegState(!IsStore);
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if (i + 1 == e) {
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SOffsetRegState |= getKillRegState(Scavenged);
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// The last implicit use carries the "Kill" flag.
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SrcDstRegState |= getKillRegState(IsKill);
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}
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BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
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.addReg(SubReg, getDefRegState(!IsStore))
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@ -464,10 +470,9 @@ void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
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.addImm(0) // glc
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.addImm(0) // slc
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.addImm(0) // tfe
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.addReg(Value, RegState::Implicit | getDefRegState(!IsStore))
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.addReg(Value, RegState::Implicit | SrcDstRegState)
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.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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}
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if (RanOutOfSGPRs) {
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// Subtract the offset we added to the ScratchOffset register.
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScratchOffset)
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@ -502,6 +507,9 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
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unsigned SuperReg = MI->getOperand(0).getReg();
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bool IsKill = MI->getOperand(0).isKill();
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// SubReg carries the "Kill" flag when SubReg == SuperReg.
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unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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unsigned SubReg = getPhysRegSubReg(SuperReg,
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&AMDGPU::SGPR_32RegClass, i);
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@ -513,7 +521,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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BuildMI(*MBB, MI, DL,
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TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
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Spill.VGPR)
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.addReg(SubReg)
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.addReg(SubReg, getKillRegState(IsKill))
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.addImm(Spill.Lane);
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// FIXME: Since this spills to another register instead of an actual
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@ -524,12 +532,18 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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// FIXME we should use S_STORE_DWORD here for VI.
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MachineInstrBuilder Mov
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= BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
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.addReg(SubReg);
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.addReg(SubReg, SubKillState);
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// There could be undef components of a spilled super register.
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// TODO: Can we detect this and skip the spill?
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if (NumSubRegs > 1)
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Mov.addReg(SuperReg, RegState::Implicit);
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if (NumSubRegs > 1) {
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// The last implicit use of the SuperReg carries the "Kill" flag.
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unsigned SuperKillState = 0;
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if (i + 1 == e)
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SuperKillState |= getKillRegState(IsKill);
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Mov.addReg(SuperReg, RegState::Implicit | SuperKillState);
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}
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unsigned Size = FrameInfo->getObjectSize(Index);
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unsigned Align = FrameInfo->getObjectAlignment(Index);
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@ -539,7 +553,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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= MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
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Size, Align);
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))
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.addReg(TmpReg) // src
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.addReg(TmpReg, RegState::Kill) // src
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.addFrameIndex(Index) // frame_idx
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.addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
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.addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
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@ -611,7 +625,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_V64_SAVE:
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case AMDGPU::SI_SPILL_V32_SAVE:
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buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
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TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::src),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
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FrameInfo->getObjectOffset(Index) +
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@ -625,7 +639,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_V256_RESTORE:
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case AMDGPU::SI_SPILL_V512_RESTORE: {
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buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
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TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::dst),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
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FrameInfo->getObjectOffset(Index) +
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@ -192,7 +192,7 @@ public:
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private:
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void buildScratchLoadStore(MachineBasicBlock::iterator MI,
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unsigned LoadStoreOp, unsigned Value,
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unsigned LoadStoreOp, const MachineOperand *SrcDst,
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unsigned ScratchRsrcReg, unsigned ScratchOffset,
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int64_t Offset,
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RegScavenger *RS) const;
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