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Use only one multiclass to pinsrq instructions 

llvm-svn: 107750
This commit is contained in:
Bruno Cardoso Lopes 2010-07-07 01:43:01 +00:00
parent fd6c808154
commit 3df55b2d6f
2 changed files with 20 additions and 38 deletions
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24
llvm/lib/Target/X86/X86Instr64bit.td
View File

@ -2349,27 +2349,3 @@ def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
"movq\t{$src, $dst|$dst, $src}", "movq\t{$src, $dst|$dst, $src}",
[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>; [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
//===----------------------------------------------------------------------===//
// X86-64 SSE4.1 Instructions
//===----------------------------------------------------------------------===//
let Constraints = "$src1 = $dst" in {
multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst,
(v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
OpSize, REX_W;
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst,
(v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
imm:$src3)))]>, OpSize, REX_W;
}
} // Constraints = "$src1 = $dst"
defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;

34
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -4214,25 +4214,31 @@ let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
let Constraints = "$src1 = $dst" in let Constraints = "$src1 = $dst" in
defm PINSRD : SS41I_insert32<0x22, "pinsrd">; defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
multiclass SS41I_insert64_avx<bits<8> opc, string OpcodeStr> { multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst), def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, GR64:$src2, i32i8imm:$src3), (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr, !if(Is2Addr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst, !strconcat(asm,
(v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
OpSize, REX_W; [(set VR128:$dst,
(v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
OpSize;
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst), def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i64mem:$src2, i32i8imm:$src3), (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
!strconcat(OpcodeStr, !if(Is2Addr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst, !strconcat(asm,
(v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2), "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
imm:$src3)))]>, OpSize, REX_W; [(set VR128:$dst,
(v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
imm:$src3)))]>, OpSize;
} }
let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
defm VPINSRQ : SS41I_insert64_avx<0x22, "vpinsrq">, VEX_4V, VEX_W; defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
let Constraints = "$src1 = $dst" in
defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
// insertps has a few different modes, there's the first two here below which // insertps has a few different modes, there's the first two here below which
// are optimized inserts that won't zero arbitrary elements in the destination // are optimized inserts that won't zero arbitrary elements in the destination