forked from OSchip/llvm-project
Use VLD1 in NEON extenting-load patterns instead of VLDR.
On some cores it's a bad idea for performance to mix VFP and NEON instructions and since these patterns are NEON anyway, the NEON load should be used. llvm-svn: 155630
This commit is contained in:
Tim Northover
parent
34e0f6cba2
commit
3de97b7a86
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@ -5595,47 +5595,51 @@ def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
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// Vector lengthening move with load, matching extending loads.
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// extload, zextload and sextload for a standard lengthening load. Example:
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// Lengthen_Single<"8", "i16", "i8"> = Pat<(v8i16 (extloadvi8 addrmode5:$addr))
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// (VMOVLuv8i16 (VLDRD addrmode5:$addr))>;
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// Lengthen_Single<"8", "i16", "i8"> =
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// Pat<(v8i16 (extloadvi8 addrmode6oneL32:$addr))
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// (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
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// (f64 (IMPLICIT_DEF)), (i32 0)))>;
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multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
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(VLDRD addrmode5:$addr))>;
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(VLD1LNd32 addrmode6oneL32:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0)))>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
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(VLDRD addrmode5:$addr))>;
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(VLD1LNd32 addrmode6oneL32:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0)))>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
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(VLDRD addrmode5:$addr))>;
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(VLD1LNd32 addrmode6oneL32:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0)))>;
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}
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// extload, zextload and sextload for a lengthening load which only uses
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// half the lanes available. Example:
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// Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
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// Pat<(v4i16 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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// (VLDRS addrmode5:$addr),
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// ssub_0)),
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// Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
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// (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
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// (f64 (IMPLICIT_DEF)), (i32 0))),
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// dsub_0)>;
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multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
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string InsnLanes, string InsnTy> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0)>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0)>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0)>;
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}
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@ -5645,32 +5649,32 @@ multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
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// Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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// (VLDRS addrmode5:$addr),
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// ssub_0)),
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// (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
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// (f64 (IMPLICIT_DEF)),
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// (i32 0))),
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// dsub_0)),
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// qsub_0)>;
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// dsub_0)>;
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multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
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string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
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string Insn2Ty> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0))>;
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0))>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0))>;
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0))>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0))>;
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0))>;
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}
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// extload, zextload and sextload for a lengthening load followed by another
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@ -5678,36 +5682,35 @@ multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
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// requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
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//
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// Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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// (VLDRS addrmode5:$addr),
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// ssub_0)),
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// dsub_0)),
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// dsub_0)>;
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
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// (f64 (IMPLICIT_DEF)), (i32 0))),
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// dsub_0)),
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// dsub_0)>;
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multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
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string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
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string Insn2Ty> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0)),
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0)),
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dsub_0)>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0)),
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0)),
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dsub_0)>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0)),
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0)),
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dsub_0)>;
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}
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@ -5727,18 +5730,18 @@ defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
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defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
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// Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
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def : Pat<(v2i64 (extloadvi8 addrmode5:$addr)),
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def : Pat<(v2i64 (extloadvi8 addrmode6oneL32:$addr)),
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(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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dsub_0)), dsub_0))>;
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def : Pat<(v2i64 (zextloadvi8 addrmode5:$addr)),
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(VLD1LNd32 addrmode6oneL32:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
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def : Pat<(v2i64 (zextloadvi8 addrmode6oneL32:$addr)),
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(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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dsub_0)), dsub_0))>;
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def : Pat<(v2i64 (sextloadvi8 addrmode5:$addr)),
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(VLD1LNd32 addrmode6oneL32:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
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def : Pat<(v2i64 (sextloadvi8 addrmode6oneL32:$addr)),
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(VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
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dsub_0)), dsub_0))>;
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(VLD1LNd32 addrmode6oneL32:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
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//===----------------------------------------------------------------------===//
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// Assembler aliases
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@ -20,7 +20,9 @@ define float @f(<4 x i16>* nocapture %in) {
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; CHECK: g:
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define float @g(<4 x i8>* nocapture %in) {
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; CHECK: vldr
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; Note: vld1 here is reasonably important. Mixing VFP and NEON
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; instructions is bad on some cores
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; CHECK: vld1
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; CHECK: vmovl.u8
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; CHECK: vmovl.u16
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%1 = load <4 x i8>* %in
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@ -47,7 +49,9 @@ define <4 x i8> @h(<4 x float> %v) {
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; CHECK: i:
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define <4 x i8> @i(<4 x i8>* %x) {
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; CHECK: vldr
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; Note: vld1 here is reasonably important. Mixing VFP and NEON
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; instructions is bad on some cores
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; CHECK: vld1
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; CHECK: vmovl.s8
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; CHECK: vmovl.s16
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; CHECK: vrecpe
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