forked from OSchip/llvm-project
[sanitizer] Refactor GetNextInstructionPc/GetPreviousInstructionPc
x86 uses offset 1 while most RISC architectures use offset 4. Check x86 first to prevent changes for new RISC architectures. Reviewed By: #sanitizers, vitalybuka Differential Revision: https://reviews.llvm.org/D120362
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@ -20,11 +20,10 @@
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namespace __sanitizer {
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uptr StackTrace::GetNextInstructionPc(uptr pc) {
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#if defined(__sparc__) || defined(__mips__)
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return pc + 8;
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#elif defined(__powerpc__) || defined(__arm__) || defined(__aarch64__) || \
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defined(__hexagon__)
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#if defined(__aarch64__)
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return STRIP_PAC_PC((void *)pc) + 4;
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#elif defined(__sparc__) || defined(__mips__)
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return pc + 8;
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#elif SANITIZER_RISCV64
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// Current check order is 4 -> 2 -> 6 -> 8
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u8 InsnByte = *(u8 *)(pc);
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@ -47,8 +46,10 @@ uptr StackTrace::GetNextInstructionPc(uptr pc) {
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}
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// bail-out if could not figure out the instruction size
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return 0;
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#else
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#elif SANITIZER_I386 || SANITIZER_X32 || SANITIZER_X64
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return pc + 1;
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#else
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return pc + 4;
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#endif
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}
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@ -88,9 +88,6 @@ uptr StackTrace::GetPreviousInstructionPc(uptr pc) {
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// so we return (pc-2) in that case in order to be safe.
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// For A32 mode we return (pc-4) because all instructions are 32 bit long.
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return (pc - 3) & (~1);
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#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__aarch64__)
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// PCs are always 4 byte aligned.
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return pc - 4;
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#elif defined(__sparc__) || defined(__mips__)
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return pc - 8;
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#elif SANITIZER_RISCV64
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@ -101,8 +98,10 @@ uptr StackTrace::GetPreviousInstructionPc(uptr pc) {
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// It seems difficult to figure out the exact instruction length -
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// pc - 2 seems like a safe option for the purposes of stack tracing
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return pc - 2;
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#else
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#elif SANITIZER_I386 || SANITIZER_X32 || SANITIZER_X64
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return pc - 1;
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#else
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return pc - 4;
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#endif
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}
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