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AMDGPU: Remove FixControlFlowLiveIntervals pass 

This hasn't done anything in a long time. This was
running after the the control flow pseudos were expanded,
so this would never find them. The control flow pseudo
expansion was moved to solve the problem this pass was
supposed to solve in the first place, except handling
it earlier also fixes it for fast regalloc which doesn't
use LiveIntervals.

Noticed by checking LCOV reports.

llvm-svn: 310274
This commit is contained in:
Matt Arsenault 2017-08-07 18:12:47 +00:00
parent ac102b6977
commit 3db456820d
4 changed files with 0 additions and 97 deletions
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3
llvm/lib/Target/AMDGPU/AMDGPU.h
View File

@ -141,9 +141,6 @@ ModulePass* createAMDGPUUnifyMetadataPass();
void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
extern char &AMDGPUUnifyMetadataID;
void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
extern char &SIFixControlFlowLiveIntervalsID;
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
extern char &SIOptimizeExecMaskingPreRAID;

5
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View File

@ -147,7 +147,6 @@ extern "C" void LLVMInitializeAMDGPUTarget() {
initializeSIFoldOperandsPass(*PR);
initializeSIPeepholeSDWAPass(*PR);
initializeSIShrinkInstructionsPass(*PR);
initializeSIFixControlFlowLiveIntervalsPass(*PR);
initializeSIOptimizeExecMaskingPreRAPass(*PR);
initializeSILoadStoreOptimizerPass(*PR);
initializeAMDGPUAlwaysInlinePass(*PR);
@ -803,10 +802,6 @@ void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
if (getOptLevel() > CodeGenOpt::None)
insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
// This needs to be run directly before register allocation because earlier
// passes might recompute live intervals.
insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
// This must be run immediately after phi elimination and before
// TwoAddressInstructions, otherwise the processing of the tied operand of
// SI_ELSE will introduce a copy of the tied operand source after the else.

1
llvm/lib/Target/AMDGPU/CMakeLists.txt
View File

@ -66,7 +66,6 @@ add_llvm_target(AMDGPUCodeGen
R600RegisterInfo.cpp
SIAnnotateControlFlow.cpp
SIDebuggerInsertNops.cpp
SIFixControlFlowLiveIntervals.cpp
SIFixSGPRCopies.cpp
SIFixVGPRCopies.cpp
SIFixWWMLiveness.cpp

88
llvm/lib/Target/AMDGPU/SIFixControlFlowLiveIntervals.cpp
View File

@ -1,88 +0,0 @@
//===-- SIFixControlFlowLiveIntervals.cpp - Fix CF live intervals ---------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// \brief Spilling of EXEC masks used for control flow messes up control flow
/// lowering, so mark all live intervals associated with CF instructions as
/// non-spillable.
///
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "SIInstrInfo.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;
#define DEBUG_TYPE "si-fix-cf-live-intervals"
namespace {
class SIFixControlFlowLiveIntervals : public MachineFunctionPass {
public:
static char ID;
public:
SIFixControlFlowLiveIntervals() : MachineFunctionPass(ID) {
initializeSIFixControlFlowLiveIntervalsPass(*PassRegistry::getPassRegistry());
}
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override { return "SI Fix CF Live Intervals"; }
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<LiveIntervals>();
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
} // End anonymous namespace.
INITIALIZE_PASS_BEGIN(SIFixControlFlowLiveIntervals, DEBUG_TYPE,
"SI Fix CF Live Intervals", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
INITIALIZE_PASS_END(SIFixControlFlowLiveIntervals, DEBUG_TYPE,
"SI Fix CF Live Intervals", false, false)
char SIFixControlFlowLiveIntervals::ID = 0;
char &llvm::SIFixControlFlowLiveIntervalsID = SIFixControlFlowLiveIntervals::ID;
FunctionPass *llvm::createSIFixControlFlowLiveIntervalsPass() {
return new SIFixControlFlowLiveIntervals();
}
bool SIFixControlFlowLiveIntervals::runOnMachineFunction(MachineFunction &MF) {
LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {
switch (MI.getOpcode()) {
case AMDGPU::SI_IF:
case AMDGPU::SI_ELSE:
case AMDGPU::SI_BREAK:
case AMDGPU::SI_IF_BREAK:
case AMDGPU::SI_ELSE_BREAK:
case AMDGPU::SI_END_CF: {
unsigned Reg = MI.getOperand(0).getReg();
LIS->getInterval(Reg).markNotSpillable();
break;
}
default:
break;
}
}
}
return false;
}