forked from OSchip/llvm-project
parent
1d107725a3
commit
3d846501fb
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@ -3054,33 +3054,6 @@ unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
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return SGPRReg;
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}
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void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
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const MachineFunction &MF) const {
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int End = getIndirectIndexEnd(MF);
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int Begin = getIndirectIndexBegin(MF);
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if (End == -1)
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return;
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for (int Index = Begin; Index <= End; ++Index)
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Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
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for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
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Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
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for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
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Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
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for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
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Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
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for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
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Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
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for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
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Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
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}
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MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
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unsigned OperandName) const {
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int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
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@ -475,12 +475,6 @@ public:
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const TargetRegisterClass *getIndirectAddrRegClass() const override;
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void reserveIndirectRegisters(BitVector &Reserved,
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const MachineFunction &MF) const;
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void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
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unsigned SavReg, unsigned IndexReg) const;
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void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
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int Count) const;
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