From 3d76824b7f493e722ae4c160b47978834226c43c Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Mon, 4 May 2020 17:41:08 +0100
Subject: [PATCH] [AMDGPU] Better support for VMEM soft clauses in
 GCNHazardRecognizer

VMEM soft clauses only contain VMEM and FLAT instructions. Teaching
GCNHazardRecognizer::checkSoftClauseHazards that other kinds of
instructions will naturally break the clause means there are far fewer
cases where it has to insert an s_nop instruction to forcibly break the
clause.

Differential Revision: https://reviews.llvm.org/D79353
---
 .../lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 10 +++++++-
 .../llvm.amdgcn.image.load.1d.d16.ll          | 24 -------------------
 .../llvm.amdgcn.image.store.2d.d16.ll         |  6 -----
 .../AMDGPU/break-vmem-soft-clauses.mir        |  3 ---
 .../llvm.amdgcn.image.sample.d16.dim.ll       |  8 -------
 llvm/test/CodeGen/AMDGPU/memory_clause.ll     | 24 -------------------
 6 files changed, 9 insertions(+), 66 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 3ef5a77af45e..02a44f929217 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -486,6 +486,14 @@ void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) {
   addRegsToSet(TRI, MI.uses(), ClauseUses);
 }
 
+static bool breaksSMEMSoftClause(MachineInstr *MI) {
+  return !SIInstrInfo::isSMRD(*MI);
+}
+
+static bool breaksVMEMSoftClause(MachineInstr *MI) {
+  return !SIInstrInfo::isVMEM(*MI) && !SIInstrInfo::isFLAT(*MI);
+}
+
 int GCNHazardRecognizer::checkSoftClauseHazards(MachineInstr *MEM) {
   // SMEM soft clause are only present on VI+, and only matter if xnack is
   // enabled.
@@ -512,7 +520,7 @@ int GCNHazardRecognizer::checkSoftClauseHazards(MachineInstr *MEM) {
     if (!MI)
       break;
 
-    if (IsSMRD != SIInstrInfo::isSMRD(*MI))
+    if (IsSMRD ? breaksSMEMSoftClause(MI) : breaksVMEMSoftClause(MI))
       break;
 
     addClauseInst(*MI);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
index bfb2c84f6c02..18aa54dcf827 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
@@ -29,8 +29,6 @@ define amdgpu_ps half @load_1d_f16_x(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v0, v0, s[0:7] dmask:0x1 unorm d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    ; return to shader part epilog
@@ -92,8 +90,6 @@ define amdgpu_ps half @load_1d_f16_y(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v0, v0, s[0:7] dmask:0x2 unorm d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    ; return to shader part epilog
@@ -155,8 +151,6 @@ define amdgpu_ps half @load_1d_f16_z(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v0, v0, s[0:7] dmask:0x4 unorm d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    ; return to shader part epilog
@@ -218,8 +212,6 @@ define amdgpu_ps half @load_1d_f16_w(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v0, v0, s[0:7] dmask:0x8 unorm d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    ; return to shader part epilog
@@ -284,8 +276,6 @@ define amdgpu_ps <2 x half> @load_1d_v2f16_xy(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v0, v0, s[0:7] dmask:0x3 unorm d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    ; return to shader part epilog
@@ -350,8 +340,6 @@ define amdgpu_ps <2 x half> @load_1d_v2f16_xz(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v0, v0, s[0:7] dmask:0x5 unorm d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    ; return to shader part epilog
@@ -416,8 +404,6 @@ define amdgpu_ps <2 x half> @load_1d_v2f16_xw(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v0, v0, s[0:7] dmask:0x9 unorm d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    ; return to shader part epilog
@@ -482,8 +468,6 @@ define amdgpu_ps <2 x half> @load_1d_v2f16_yz(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v0, v0, s[0:7] dmask:0x6 unorm d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    ; return to shader part epilog
@@ -558,8 +542,6 @@ define amdgpu_ps <4 x half> @load_1d_v4f16_xyzw(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v[0:1], v0, s[0:7] dmask:0xf unorm d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    ; return to shader part epilog
@@ -622,8 +604,6 @@ define amdgpu_ps float @load_1d_f16_tfe_dmask_x(<8 x i32> inreg %rsrc, i32 %s) {
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v[0:1], v0, s[0:7] dmask:0x1 unorm tfe d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    v_mov_b32_e32 v0, v1
@@ -691,8 +671,6 @@ define amdgpu_ps float @load_1d_v2f16_tfe_dmask_xy(<8 x i32> inreg %rsrc, i32 %s
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v[0:1], v0, s[0:7] dmask:0x3 unorm tfe d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    v_mov_b32_e32 v0, v1
@@ -768,8 +746,6 @@ define amdgpu_ps float @load_1d_v4f16_tfe_dmask_xyzw(<8 x i32> inreg %rsrc, i32
 ; GFX8-PACKED-NEXT:    s_mov_b32 s5, s7
 ; GFX8-PACKED-NEXT:    s_mov_b32 s6, s8
 ; GFX8-PACKED-NEXT:    s_mov_b32 s7, s9
-; GFX8-PACKED-NEXT:    s_nop 0
-; GFX8-PACKED-NEXT:    s_nop 0
 ; GFX8-PACKED-NEXT:    image_load v[0:1], v0, s[0:7] dmask:0x10 unorm tfe d16
 ; GFX8-PACKED-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-PACKED-NEXT:    v_mov_b32_e32 v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
index a192b372995b..d04469bf3e2e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
@@ -26,8 +26,6 @@ define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ha
 ; PACKED-NEXT:    s_mov_b32 s5, s7
 ; PACKED-NEXT:    s_mov_b32 s6, s8
 ; PACKED-NEXT:    s_mov_b32 s7, s9
-; PACKED-NEXT:    s_nop 0
-; PACKED-NEXT:    s_nop 0
 ; PACKED-NEXT:    image_store v2, v[0:1], s[0:7] dmask:0x1 unorm
 ; PACKED-NEXT:    s_endpgm
   call void @llvm.amdgcn.image.store.2d.f16.i32(half %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -59,8 +57,6 @@ define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
 ; PACKED-NEXT:    s_mov_b32 s5, s7
 ; PACKED-NEXT:    s_mov_b32 s6, s8
 ; PACKED-NEXT:    s_mov_b32 s7, s9
-; PACKED-NEXT:    s_nop 0
-; PACKED-NEXT:    s_nop 0
 ; PACKED-NEXT:    image_store v2, v[0:1], s[0:7] dmask:0x3 unorm
 ; PACKED-NEXT:    s_endpgm
   call void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -102,8 +98,6 @@ define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
 ; PACKED-NEXT:    s_mov_b32 s5, s7
 ; PACKED-NEXT:    s_mov_b32 s6, s8
 ; PACKED-NEXT:    s_mov_b32 s7, s9
-; PACKED-NEXT:    s_nop 0
-; PACKED-NEXT:    s_nop 0
 ; PACKED-NEXT:    image_store v[2:3], v[0:1], s[0:7] dmask:0xf unorm
 ; PACKED-NEXT:    s_endpgm
   call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir b/llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
index 4ac48b1133aa..8e9aaa703581 100644
--- a/llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
+++ b/llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
@@ -308,7 +308,6 @@ body: |
     ; GCN-LABEL: name: valu_inst_breaks_clause
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr8 = V_MOV_B32_e32 0, implicit $exec
-    ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: S_ENDPGM 0
 
@@ -327,7 +326,6 @@ body: |
     ; GCN-LABEL: name: salu_inst_breaks_clause
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $sgpr8 = S_MOV_B32 0
-    ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: S_ENDPGM 0
 
@@ -345,7 +343,6 @@ body: |
     ; GCN-LABEL: name: ds_inst_breaks_clause
     ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec
-    ; XNACK-NEXT: S_NOP 0
     ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
     ; GCN-NEXT: S_ENDPGM 0
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
index 192dd233eb20..8a358ee59c96 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
@@ -19,7 +19,6 @@ define amdgpu_ps half @image_sample_2d_f16(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX81-NEXT:    s_mov_b64 s[12:13], exec
 ; GFX81-NEXT:    s_wqm_b64 exec, exec
 ; GFX81-NEXT:    s_and_b64 exec, exec, s[12:13]
-; GFX81-NEXT:    s_nop 0
 ; GFX81-NEXT:    image_sample v0, v[0:1], s[0:7], s[8:11] dmask:0x1 d16
 ; GFX81-NEXT:    s_waitcnt vmcnt(0)
 ; GFX81-NEXT:    ; return to shader part epilog
@@ -73,12 +72,9 @@ define amdgpu_ps half @image_sample_2d_f16_tfe(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX81-NEXT:    v_mov_b32_e32 v5, s13
 ; GFX81-NEXT:    v_mov_b32_e32 v3, v2
 ; GFX81-NEXT:    s_and_b64 exec, exec, s[14:15]
-; GFX81-NEXT:    s_nop 0
 ; GFX81-NEXT:    image_sample v[2:3], v[0:1], s[0:7], s[8:11] dmask:0x1 tfe d16
 ; GFX81-NEXT:    s_waitcnt vmcnt(0)
 ; GFX81-NEXT:    v_mov_b32_e32 v0, v2
-; GFX81-NEXT:    s_nop 0
-; GFX81-NEXT:    s_nop 0
 ; GFX81-NEXT:    flat_store_dword v[4:5], v3
 ; GFX81-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX81-NEXT:    ; return to shader part epilog
@@ -173,8 +169,6 @@ define amdgpu_ps <2 x float> @image_sample_c_d_1d_v2f16_tfe(<8 x i32> inreg %rsr
 ; GFX81:       ; %bb.0: ; %main_body
 ; GFX81-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX81-NEXT:    v_mov_b32_e32 v5, v4
-; GFX81-NEXT:    s_nop 0
-; GFX81-NEXT:    s_nop 0
 ; GFX81-NEXT:    image_sample_c_d v[4:5], v[0:3], s[0:7], s[8:11] dmask:0x3 tfe d16
 ; GFX81-NEXT:    s_waitcnt vmcnt(0)
 ; GFX81-NEXT:    v_mov_b32_e32 v0, v4
@@ -231,7 +225,6 @@ define amdgpu_ps <2 x float> @image_sample_b_2d_v4f16(<8 x i32> inreg %rsrc, <4
 ; GFX81-NEXT:    s_mov_b64 s[12:13], exec
 ; GFX81-NEXT:    s_wqm_b64 exec, exec
 ; GFX81-NEXT:    s_and_b64 exec, exec, s[12:13]
-; GFX81-NEXT:    s_nop 0
 ; GFX81-NEXT:    image_sample_b v[0:1], v[0:2], s[0:7], s[8:11] dmask:0xf d16
 ; GFX81-NEXT:    s_waitcnt vmcnt(0)
 ; GFX81-NEXT:    ; return to shader part epilog
@@ -288,7 +281,6 @@ define amdgpu_ps <4 x float> @image_sample_b_2d_v4f16_tfe(<8 x i32> inreg %rsrc,
 ; GFX81-NEXT:    v_mov_b32_e32 v4, v3
 ; GFX81-NEXT:    v_mov_b32_e32 v5, v3
 ; GFX81-NEXT:    s_and_b64 exec, exec, s[12:13]
-; GFX81-NEXT:    s_nop 0
 ; GFX81-NEXT:    image_sample_b v[3:5], v[0:2], s[0:7], s[8:11] dmask:0xf tfe d16
 ; GFX81-NEXT:    s_waitcnt vmcnt(0)
 ; GFX81-NEXT:    v_mov_b32_e32 v0, v3
diff --git a/llvm/test/CodeGen/AMDGPU/memory_clause.ll b/llvm/test/CodeGen/AMDGPU/memory_clause.ll
index 15a8e9283e38..5a435f01925c 100644
--- a/llvm/test/CodeGen/AMDGPU/memory_clause.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory_clause.ll
@@ -8,16 +8,13 @@ define amdgpu_kernel void @vector_clause(<4 x i32> addrspace(1)* noalias nocaptu
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
 ; GCN-NEXT:    v_mov_b32_e32 v17, 0
 ; GCN-NEXT:    v_lshlrev_b32_e32 v16, 4, v0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_load_dwordx4 v[0:3], v[16:17], s[2:3]
 ; GCN-NEXT:    global_load_dwordx4 v[4:7], v[16:17], s[2:3] offset:16
 ; GCN-NEXT:    global_load_dwordx4 v[8:11], v[16:17], s[2:3] offset:32
 ; GCN-NEXT:    global_load_dwordx4 v[12:15], v[16:17], s[2:3] offset:48
 ; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    s_waitcnt vmcnt(3)
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_store_dwordx4 v[16:17], v[0:3], s[4:5]
 ; GCN-NEXT:    s_waitcnt vmcnt(3)
 ; GCN-NEXT:    global_store_dwordx4 v[16:17], v[4:7], s[4:5] offset:16
@@ -74,8 +71,6 @@ define amdgpu_kernel void @scalar_clause(<4 x i32> addrspace(1)* noalias nocaptu
 ; GCN-NEXT:    v_mov_b32_e32 v5, s5
 ; GCN-NEXT:    v_mov_b32_e32 v6, s6
 ; GCN-NEXT:    v_mov_b32_e32 v7, s7
-; GCN-NEXT:    s_nop 0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_store_dwordx4 v[12:13], v[0:3], off
 ; GCN-NEXT:    global_store_dwordx4 v[12:13], v[4:7], off offset:16
 ; GCN-NEXT:    v_mov_b32_e32 v0, s12
@@ -85,8 +80,6 @@ define amdgpu_kernel void @scalar_clause(<4 x i32> addrspace(1)* noalias nocaptu
 ; GCN-NEXT:    v_mov_b32_e32 v1, s13
 ; GCN-NEXT:    v_mov_b32_e32 v2, s14
 ; GCN-NEXT:    v_mov_b32_e32 v3, s15
-; GCN-NEXT:    s_nop 0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_store_dwordx4 v[12:13], v[8:11], off offset:32
 ; GCN-NEXT:    global_store_dwordx4 v[12:13], v[0:3], off offset:48
 ; GCN-NEXT:    s_endpgm
@@ -116,8 +109,6 @@ define void @mubuf_clause(<4 x i32> addrspace(5)* noalias nocapture readonly %ar
 ; GCN-NEXT:    v_lshlrev_b32_e32 v2, 4, v2
 ; GCN-NEXT:    v_add_u32_e32 v0, v0, v2
 ; GCN-NEXT:    v_add_u32_e32 v1, v1, v2
-; GCN-NEXT:    s_nop 0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    buffer_load_dword v6, v0, s[0:3], 0 offen offset:20
 ; GCN-NEXT:    buffer_load_dword v7, v0, s[0:3], 0 offen offset:24
 ; GCN-NEXT:    buffer_load_dword v8, v0, s[0:3], 0 offen offset:28
@@ -134,11 +125,9 @@ define void @mubuf_clause(<4 x i32> addrspace(5)* noalias nocapture readonly %ar
 ; GCN-NEXT:    buffer_load_dword v4, v0, s[0:3], 0 offen offset:8
 ; GCN-NEXT:    buffer_load_dword v5, v0, s[0:3], 0 offen offset:12
 ; GCN-NEXT:    s_nop 0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    buffer_load_dword v0, v0, s[0:3], 0 offen offset:16
 ; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    s_waitcnt vmcnt(4)
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    buffer_store_dword v2, v1, s[0:3], 0 offen
 ; GCN-NEXT:    s_waitcnt vmcnt(4)
 ; GCN-NEXT:    buffer_store_dword v3, v1, s[0:3], 0 offen offset:4
@@ -192,20 +181,15 @@ define amdgpu_kernel void @vector_clause_indirect(i64 addrspace(1)* noalias noca
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_load_dwordx2 v[8:9], v[0:1], s[2:3]
 ; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_load_dwordx4 v[0:3], v[8:9], off
 ; GCN-NEXT:    global_load_dwordx4 v[4:7], v[8:9], off offset:16
 ; GCN-NEXT:    v_mov_b32_e32 v9, s5
 ; GCN-NEXT:    v_mov_b32_e32 v8, s4
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    s_waitcnt vmcnt(1)
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_store_dwordx4 v[8:9], v[0:3], off
 ; GCN-NEXT:    s_waitcnt vmcnt(1)
 ; GCN-NEXT:    global_store_dwordx4 v[8:9], v[4:7], off offset:16
@@ -230,15 +214,11 @@ define void @load_global_d16_hi(i16 addrspace(1)* %in, i16 %reg, <2 x i16> addrs
 ; GCN:       ; %bb.0: ; %entry
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mov_b32_e32 v5, v2
-; GCN-NEXT:    s_nop 0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_load_short_d16_hi v5, v[0:1], off
 ; GCN-NEXT:    s_nop 0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_load_short_d16_hi v2, v[0:1], off offset:64
 ; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    s_waitcnt vmcnt(1)
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_store_dword v[3:4], v5, off
 ; GCN-NEXT:    s_waitcnt vmcnt(1)
 ; GCN-NEXT:    global_store_dword v[3:4], v2, off offset:128
@@ -263,15 +243,11 @@ define void @load_global_d16_lo(i16 addrspace(1)* %in, i32 %reg, <2 x i16> addrs
 ; GCN:       ; %bb.0: ; %entry
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mov_b32_e32 v5, v2
-; GCN-NEXT:    s_nop 0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_load_short_d16 v5, v[0:1], off
 ; GCN-NEXT:    s_nop 0
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_load_short_d16 v2, v[0:1], off offset:64
 ; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    s_waitcnt vmcnt(1)
-; GCN-NEXT:    s_nop 0
 ; GCN-NEXT:    global_store_dword v[3:4], v5, off
 ; GCN-NEXT:    s_waitcnt vmcnt(1)
 ; GCN-NEXT:    global_store_dword v[3:4], v2, off offset:128