forked from OSchip/llvm-project
[Power9] Add __float128 support for compare operations
Added handling for the select f128. Differential Revision: https://reviews.llvm.org/D48294 llvm-svn: 336548
This commit is contained in:
Stefan Pintilie
parent
813b21e33a
commit
3d76326d24
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@ -3617,9 +3617,12 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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}
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} else if (LHS.getValueType() == MVT::f32) {
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Opc = PPC::FCMPUS;
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} else {
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assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
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} else if (LHS.getValueType() == MVT::f64) {
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Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
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} else {
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assert(LHS.getValueType() == MVT::f128 && "Unknown vt!");
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assert(PPCSubTarget->hasVSX() && "__float128 requires VSX");
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Opc = PPC::XSCMPUQP;
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}
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return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
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}
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@ -4564,6 +4567,8 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
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SelectCCOp = PPC::SELECT_CC_VSFRC;
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else
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SelectCCOp = PPC::SELECT_CC_F8;
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else if (N->getValueType(0) == MVT::f128)
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SelectCCOp = PPC::SELECT_CC_F16;
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else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
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SelectCCOp = PPC::SELECT_CC_QFRC;
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else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
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@ -810,6 +810,13 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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for (MVT FPT : MVT::fp_valuetypes())
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setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
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setOperationAction(ISD::FMA, MVT::f128, Legal);
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setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
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setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
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setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
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setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
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setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
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setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
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setOperationAction(ISD::SELECT, MVT::f128, Expand);
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setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
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setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
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setTruncStoreAction(MVT::f128, MVT::f64, Expand);
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@ -10206,6 +10213,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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MI.getOpcode() == PPC::SELECT_CC_I8 ||
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MI.getOpcode() == PPC::SELECT_CC_F4 ||
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MI.getOpcode() == PPC::SELECT_CC_F8 ||
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MI.getOpcode() == PPC::SELECT_CC_F16 ||
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MI.getOpcode() == PPC::SELECT_CC_QFRC ||
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MI.getOpcode() == PPC::SELECT_CC_QSRC ||
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MI.getOpcode() == PPC::SELECT_CC_QBRC ||
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@ -10217,6 +10225,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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MI.getOpcode() == PPC::SELECT_I8 ||
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MI.getOpcode() == PPC::SELECT_F4 ||
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MI.getOpcode() == PPC::SELECT_F8 ||
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MI.getOpcode() == PPC::SELECT_F16 ||
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MI.getOpcode() == PPC::SELECT_QFRC ||
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MI.getOpcode() == PPC::SELECT_QSRC ||
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MI.getOpcode() == PPC::SELECT_QBRC ||
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@ -10252,6 +10261,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 ||
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MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 ||
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MI.getOpcode() == PPC::SELECT_F16 ||
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MI.getOpcode() == PPC::SELECT_QFRC ||
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MI.getOpcode() == PPC::SELECT_QSRC ||
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MI.getOpcode() == PPC::SELECT_QBRC ||
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@ -1216,6 +1216,9 @@ let usesCustomInserter = 1, // Expanded after instruction selection.
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def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
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i32imm:$BROPC), "#SELECT_CC_F8",
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[]>;
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def SELECT_CC_F16 : Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
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i32imm:$BROPC), "#SELECT_CC_F16",
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[]>;
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def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
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i32imm:$BROPC), "#SELECT_CC_VRRC",
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[]>;
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@ -1234,6 +1237,9 @@ let usesCustomInserter = 1, // Expanded after instruction selection.
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def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
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f8rc:$T, f8rc:$F), "#SELECT_F8",
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[(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
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def SELECT_F16 : Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
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vrrc:$T, vrrc:$F), "#SELECT_F16",
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[(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>;
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def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
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vrrc:$T, vrrc:$F), "#SELECT_VRRC",
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[(set v4i32:$dst,
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@ -3622,6 +3628,37 @@ defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
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defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
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(EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
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// SETCC for f128.
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def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOLT)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
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def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETLT)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
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def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOGT)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
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def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETGT)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
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def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOEQ)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
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def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETEQ)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
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def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETUO)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>;
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defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUGE)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
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defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETGE)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
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defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETULE)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
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defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETLE)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
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defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUNE)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
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defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETNE)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
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defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETO)),
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(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>;
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// match select on i1 variables:
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def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
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(CROR (CRAND $cond , $tval),
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@ -3746,6 +3783,27 @@ def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
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def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
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(SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)),
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(SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)),
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(SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)),
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(SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)),
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(SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)),
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(SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)),
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(SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)),
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(SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)),
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(SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)),
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(SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)),
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(SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>;
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def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
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(SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
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@ -0,0 +1,225 @@
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s | FileCheck %s
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@a_qp = common global fp128 0xL00000000000000000000000000000000, align 16
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@b_qp = common global fp128 0xL00000000000000000000000000000000, align 16
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; Function Attrs: noinline nounwind optnone
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define signext i32 @greater_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ogt fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: greater_qp
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; CHECK: xscmpuqp
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 1
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @less_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp olt fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: less_qp
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; CHECK: xscmpuqp
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 0
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @greater_eq_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp oge fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: greater_eq_qp
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; CHECK: xscmpuqp
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; CHECK: cror [[REG:[0-9]+]], {{[0-9]+}}, 0
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @less_eq_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ole fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: less_eq_qp
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; CHECK: xscmpuqp
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; CHECK: cror [[REG:[0-9]+]], {{[0-9]+}}, 1
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @equal_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp oeq fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: equal_qp
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; CHECK: xscmpuqp
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 2
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_greater_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ogt fp128 %0, %1
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%lnot = xor i1 %cmp, true
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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; CHECK-LABEL: not_greater_qp
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; CHECK: xscmpuqp
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 1
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_less_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp olt fp128 %0, %1
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%lnot = xor i1 %cmp, true
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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; CHECK-LABEL: not_less_qp
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; CHECK: xscmpuqp
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 0
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_greater_eq_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp oge fp128 %0, %1
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%lnot = xor i1 %cmp, true
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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; CHECK-LABEL: not_greater_eq_qp
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; CHECK: xscmpuqp
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; CHECK: crnor [[REG:[0-9]+]], 0, {{[0-9]+}}
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_less_eq_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ole fp128 %0, %1
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%lnot = xor i1 %cmp, true
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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; CHECK-LABEL: not_less_eq_qp
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; CHECK: xscmpuqp
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; CHECK: crnor [[REG:[0-9]+]], 1, {{[0-9]+}}
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_equal_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp une fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: not_equal_qp
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; CHECK: xscmpuqp
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; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 2
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readonly
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define fp128 @greater_sel_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ogt fp128 %0, %1
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%cond = select i1 %cmp, fp128 %0, fp128 %1
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ret fp128 %cond
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; CHECK-LABEL: greater_sel_qp
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; CHECK: xscmpuqp [[REG:[0-9]+]]
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; CHECK: bgtlr [[REG]]
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define fp128 @less_sel_qp() {
|
||||
entry:
|
||||
%0 = load fp128, fp128* @a_qp, align 16
|
||||
%1 = load fp128, fp128* @b_qp, align 16
|
||||
%cmp = fcmp olt fp128 %0, %1
|
||||
%cond = select i1 %cmp, fp128 %0, fp128 %1
|
||||
ret fp128 %cond
|
||||
; CHECK-LABEL: less_sel_qp
|
||||
; CHECK: xscmpuqp [[REG:[0-9]+]]
|
||||
; CHECK: bltlr [[REG]]
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
; Function Attrs: noinline nounwind optnone
|
||||
define fp128 @greater_eq_sel_qp() {
|
||||
entry:
|
||||
%0 = load fp128, fp128* @a_qp, align 16
|
||||
%1 = load fp128, fp128* @b_qp, align 16
|
||||
%cmp = fcmp oge fp128 %0, %1
|
||||
%cond = select i1 %cmp, fp128 %0, fp128 %1
|
||||
ret fp128 %cond
|
||||
; CHECK-LABEL: greater_eq_sel_qp
|
||||
; CHECK: xscmpuqp
|
||||
; CHECK: crnor [[REG:[0-9]+]], {{[0-9]+}}, 0
|
||||
; CHECK: bclr {{[0-9]+}}, [[REG]]
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
; Function Attrs: noinline nounwind optnone
|
||||
define fp128 @less_eq_sel_qp() {
|
||||
entry:
|
||||
%0 = load fp128, fp128* @a_qp, align 16
|
||||
%1 = load fp128, fp128* @b_qp, align 16
|
||||
%cmp = fcmp ole fp128 %0, %1
|
||||
%cond = select i1 %cmp, fp128 %0, fp128 %1
|
||||
ret fp128 %cond
|
||||
; CHECK-LABEL: less_eq_sel_qp
|
||||
; CHECK: xscmpuqp
|
||||
; CHECK: crnor [[REG:[0-9]+]], {{[0-9]+}}, 1
|
||||
; CHECK: bclr {{[0-9]+}}, [[REG]]
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
; Function Attrs: noinline nounwind optnone
|
||||
define fp128 @equal_sel_qp() {
|
||||
entry:
|
||||
%0 = load fp128, fp128* @a_qp, align 16
|
||||
%1 = load fp128, fp128* @b_qp, align 16
|
||||
%cmp = fcmp oeq fp128 %0, %1
|
||||
%cond = select i1 %cmp, fp128 %0, fp128 %1
|
||||
ret fp128 %cond
|
||||
; CHECK-LABEL: equal_sel_qp
|
||||
; CHECK: xscmpuqp [[REG:[0-9]+]]
|
||||
; CHECK: beqlr [[REG]]
|
||||
; CHECK: blr
|
||||
}
|
||||
Loading…
Reference in New Issue