forked from OSchip/llvm-project
Add a base class for Mips TargetMachines and add Mips64 TargetMachines.
llvm-svn: 140233
This commit is contained in:
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cf24656ea4
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3d673cc323
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@ -18,7 +18,8 @@ using namespace llvm;
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MipsMCAsmInfo::MipsMCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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if (TheTriple.getArch() == Triple::mips)
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if ((TheTriple.getArch() == Triple::mips) ||
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(TheTriple.getArch() == Triple::mips64))
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IsLittleEndian = false;
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AlignmentIsInBytes = false;
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@ -81,27 +81,49 @@ extern "C" void LLVMInitializeMipsTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo);
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RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo);
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RegisterMCAsmInfoFn A(TheMips64Target, createMipsMCAsmInfo);
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RegisterMCAsmInfoFn B(TheMips64elTarget, createMipsMCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget,
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createMipsMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget,
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createMipsMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(TheMips64Target,
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createMipsMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(TheMips64elTarget,
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createMipsMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheMipselTarget, createMipsMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheMips64Target, createMipsMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheMips64elTarget, createMipsMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheMipsTarget, createMipsMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheMipselTarget, createMipsMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheMips64Target, createMipsMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheMips64elTarget,
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createMipsMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
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createMipsMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheMipselTarget,
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createMipsMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheMips64Target,
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createMipsMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheMips64elTarget,
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createMipsMCSubtargetInfo);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(TheMipsTarget,
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createMipsMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
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createMipsMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheMips64Target,
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createMipsMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheMips64elTarget,
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createMipsMCInstPrinter);
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}
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@ -21,6 +21,8 @@ class StringRef;
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extern Target TheMipsTarget;
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extern Target TheMipselTarget;
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extern Target TheMips64Target;
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extern Target TheMips64elTarget;
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} // End llvm namespace
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@ -455,4 +455,6 @@ void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
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extern "C" void LLVMInitializeMipsAsmPrinter() {
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RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
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RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
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RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
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RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);
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}
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@ -19,8 +19,10 @@ using namespace llvm;
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extern "C" void LLVMInitializeMipsTarget() {
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// Register the target.
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RegisterTargetMachine<MipsTargetMachine> X(TheMipsTarget);
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RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
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RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
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RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target);
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RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget);
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}
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// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
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@ -34,23 +36,45 @@ MipsTargetMachine::
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MipsTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM,
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bool isLittle=false):
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bool isLittle):
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LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
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Subtarget(TT, CPU, FS, isLittle),
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DataLayout(isLittle ?
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std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
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std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
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(Subtarget.isABI_N64() ?
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"e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
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"e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
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(Subtarget.isABI_N64() ?
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"E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
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"E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
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InstrInfo(*this),
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FrameLowering(Subtarget),
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TLInfo(*this), TSInfo(*this), JITInfo() {
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}
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MipsebTargetMachine::
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MipsebTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM) :
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MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
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MipselTargetMachine::
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MipselTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM) :
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MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
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Mips64ebTargetMachine::
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Mips64ebTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM) :
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MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
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Mips64elTargetMachine::
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Mips64elTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM) :
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MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsTargetMachine::
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@ -80,7 +80,16 @@ namespace llvm {
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};
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/// MipselTargetMachine - Mipsel target machine.
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/// MipsebTargetMachine - Mips32 big endian target machine.
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///
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class MipsebTargetMachine : public MipsTargetMachine {
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public:
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MipsebTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM);
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};
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/// MipselTargetMachine - Mips32 little endian target machine.
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///
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class MipselTargetMachine : public MipsTargetMachine {
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public:
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@ -89,6 +98,23 @@ public:
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Reloc::Model RM, CodeModel::Model CM);
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};
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/// MipsebTargetMachine - Mips32 big endian target machine.
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///
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class Mips64ebTargetMachine : public MipsTargetMachine {
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public:
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Mips64ebTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM);
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};
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/// MipselTargetMachine - Mips32 little endian target machine.
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///
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class Mips64elTargetMachine : public MipsTargetMachine {
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public:
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Mips64elTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM);
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};
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} // End llvm namespace
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#endif
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@ -13,6 +13,7 @@
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using namespace llvm;
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Target llvm::TheMipsTarget, llvm::TheMipselTarget;
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Target llvm::TheMips64Target, llvm::TheMips64elTarget;
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extern "C" void LLVMInitializeMipsTargetInfo() {
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RegisterTarget<Triple::mips,
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@ -20,4 +21,11 @@ extern "C" void LLVMInitializeMipsTargetInfo() {
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RegisterTarget<Triple::mipsel,
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/*HasJIT=*/true> Y(TheMipselTarget, "mipsel", "Mipsel");
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RegisterTarget<Triple::mips64,
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/*HasJIT=*/false> A(TheMips64Target, "mips64", "Mips64 [experimental]");
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RegisterTarget<Triple::mips64el,
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/*HasJIT=*/false> B(TheMips64elTarget,
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"mips64el", "Mips64el [experimental]");
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}
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