maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Add a base class for Mips TargetMachines and add Mips64 TargetMachines. 

llvm-svn: 140233
This commit is contained in:
Akira Hatanaka 2011-09-21 03:00:58 +00:00
parent cf24656ea4
commit 3d673cc323
7 changed files with 92 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
View File

@ -18,7 +18,8 @@ using namespace llvm;
MipsMCAsmInfo::MipsMCAsmInfo(const Target &T, StringRef TT) {
Triple TheTriple(TT);
if (TheTriple.getArch() == Triple::mips)
if ((TheTriple.getArch() == Triple::mips) ||
(TheTriple.getArch() == Triple::mips64))
IsLittleEndian = false;
AlignmentIsInBytes = false;

22
llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -81,27 +81,49 @@ extern "C" void LLVMInitializeMipsTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo);
RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo);
RegisterMCAsmInfoFn A(TheMips64Target, createMipsMCAsmInfo);
RegisterMCAsmInfoFn B(TheMips64elTarget, createMipsMCAsmInfo);
// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget,
createMipsMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget,
createMipsMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheMips64Target,
createMipsMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheMips64elTarget,
createMipsMCCodeGenInfo);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheMipselTarget, createMipsMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheMips64Target, createMipsMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheMips64elTarget, createMipsMCInstrInfo);
// Register the MC register info.
TargetRegistry::RegisterMCRegInfo(TheMipsTarget, createMipsMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheMipselTarget, createMipsMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheMips64Target, createMipsMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheMips64elTarget,
createMipsMCRegisterInfo);
// Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
createMipsMCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheMipselTarget,
createMipsMCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheMips64Target,
createMipsMCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheMips64elTarget,
createMipsMCSubtargetInfo);
// Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(TheMipsTarget,
createMipsMCInstPrinter);
TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
createMipsMCInstPrinter);
TargetRegistry::RegisterMCInstPrinter(TheMips64Target,
createMipsMCInstPrinter);
TargetRegistry::RegisterMCInstPrinter(TheMips64elTarget,
createMipsMCInstPrinter);
}

2
llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
View File

@ -21,6 +21,8 @@ class StringRef;
extern Target TheMipsTarget;
extern Target TheMipselTarget;
extern Target TheMips64Target;
extern Target TheMips64elTarget;
} // End llvm namespace

2
llvm/lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -455,4 +455,6 @@ void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
extern "C" void LLVMInitializeMipsAsmPrinter() {
RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);
}

32
llvm/lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -19,8 +19,10 @@ using namespace llvm;
extern "C" void LLVMInitializeMipsTarget() {
// Register the target.
RegisterTargetMachine<MipsTargetMachine> X(TheMipsTarget);
RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target);
RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget);
}
// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
@ -34,23 +36,45 @@ MipsTargetMachine::
MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM,
bool isLittle=false):
bool isLittle):
LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
Subtarget(TT, CPU, FS, isLittle),
DataLayout(isLittle ?
std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
(Subtarget.isABI_N64() ?
"e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
"e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
(Subtarget.isABI_N64() ?
"E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
"E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
InstrInfo(*this),
FrameLowering(Subtarget),
TLInfo(*this), TSInfo(*this), JITInfo() {
}
MipsebTargetMachine::
MipsebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) :
MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
MipselTargetMachine::
MipselTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) :
MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
Mips64ebTargetMachine::
Mips64ebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) :
MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
Mips64elTargetMachine::
Mips64elTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) :
MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
// Install an instruction selector pass using
// the ISelDag to gen Mips code.
bool MipsTargetMachine::

28
llvm/lib/Target/Mips/MipsTargetMachine.h
View File

@ -80,7 +80,16 @@ namespace llvm {
};
/// MipselTargetMachine - Mipsel target machine.
/// MipsebTargetMachine - Mips32 big endian target machine.
///
class MipsebTargetMachine : public MipsTargetMachine {
public:
MipsebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
};
/// MipselTargetMachine - Mips32 little endian target machine.
///
class MipselTargetMachine : public MipsTargetMachine {
public:
@ -89,6 +98,23 @@ public:
Reloc::Model RM, CodeModel::Model CM);
};
/// MipsebTargetMachine - Mips32 big endian target machine.
///
class Mips64ebTargetMachine : public MipsTargetMachine {
public:
Mips64ebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
};
/// MipselTargetMachine - Mips32 little endian target machine.
///
class Mips64elTargetMachine : public MipsTargetMachine {
public:
Mips64elTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM);
};
} // End llvm namespace
#endif

8
llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
View File

@ -13,6 +13,7 @@
using namespace llvm;
Target llvm::TheMipsTarget, llvm::TheMipselTarget;
Target llvm::TheMips64Target, llvm::TheMips64elTarget;
extern "C" void LLVMInitializeMipsTargetInfo() {
RegisterTarget<Triple::mips,
@ -20,4 +21,11 @@ extern "C" void LLVMInitializeMipsTargetInfo() {
RegisterTarget<Triple::mipsel,
/*HasJIT=*/true> Y(TheMipselTarget, "mipsel", "Mipsel");
RegisterTarget<Triple::mips64,
/*HasJIT=*/false> A(TheMips64Target, "mips64", "Mips64 [experimental]");
RegisterTarget<Triple::mips64el,
/*HasJIT=*/false> B(TheMips64elTarget,
"mips64el", "Mips64el [experimental]");
}