forked from OSchip/llvm-project
parent
5f9150b5b1
commit
3d57441e56
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@ -224,9 +224,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Cacheability support ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_v4f32_ty], []>;
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def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
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Intrinsic<[], [], []>;
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}
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@ -536,19 +533,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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llvm_v4i32_ty], []>;
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}
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// Cacheability support ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse2_movnt_dq : GCCBuiltin<"__builtin_ia32_movntdq">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_v2i64_ty], []>;
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def int_x86_sse2_movnt_pd : GCCBuiltin<"__builtin_ia32_movntpd">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_v2f64_ty], []>;
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def int_x86_sse2_movnt_i : GCCBuiltin<"__builtin_ia32_movnti">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_i32_ty], []>;
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}
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// Misc.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
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