forked from OSchip/llvm-project
AArch64: Use DeadRegisterDefinitionsPass before regalloc.
Doing this before register allocation reduces register pressure as we do not even have to allocate a register for those dead definitions. Differential Revision: https://reviews.llvm.org/D26111 llvm-svn: 287076
This commit is contained in:
Matthias Braun
parent
6b335d1948
commit
3d51cf0a2c
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@ -17,9 +17,11 @@
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-dead-defs"
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@ -32,8 +34,9 @@ namespace {
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class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
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private:
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const TargetRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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bool Changed;
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bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
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void processMachineBasicBlock(MachineBasicBlock &MBB);
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public:
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static char ID; // Pass identification, replacement for typeid.
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@ -44,11 +47,6 @@ public:
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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@ -62,15 +60,6 @@ char AArch64DeadRegisterDefinitions::ID = 0;
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INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
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AARCH64_DEAD_REG_DEF_NAME, false, false)
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bool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg(
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unsigned Reg, const MachineInstr &MI) {
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for (const MachineOperand &MO : MI.implicit_operands())
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if (MO.isReg() && MO.isDef())
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if (TRI->regsOverlap(Reg, MO.getReg()))
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return true;
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return false;
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}
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static bool usesFrameIndex(const MachineInstr &MI) {
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for (const MachineOperand &MO : MI.uses())
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if (MO.isFI())
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@ -80,6 +69,7 @@ static bool usesFrameIndex(const MachineInstr &MI) {
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void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
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MachineBasicBlock &MBB) {
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const MachineFunction &MF = *MBB.getParent();
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for (MachineInstr &MI : MBB) {
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if (usesFrameIndex(MI)) {
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// We need to skip this instruction because while it appears to have a
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@ -97,7 +87,13 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
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const MCInstrDesc &Desc = MI.getDesc();
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for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
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MachineOperand &MO = MI.getOperand(I);
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if (!MO.isReg() || !MO.isDead() || !MO.isDef())
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if (!MO.isReg() || !MO.isDef())
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continue;
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// We should not have any relevant physreg defs that are replacable by
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// zero before register allocation. So we just check for dead vreg defs.
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg) ||
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(!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
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continue;
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assert(!MO.isImplicit() && "Unexpected implicit def!");
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DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
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@ -107,28 +103,22 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
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DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
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continue;
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}
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// Don't change the register if there's an implicit def of a subreg or
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// superreg.
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if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
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DEBUG(dbgs() << " Ignoring, implicitly defines overlap reg.\n");
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continue;
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}
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// Make sure the instruction take a register class that contains
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// the zero register and replace it if so.
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const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
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unsigned NewReg;
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switch (Desc.OpInfo[I].RegClass) {
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default:
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if (RC == nullptr) {
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DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
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continue;
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case AArch64::GPR32RegClassID:
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} else if (RC->contains(AArch64::WZR))
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NewReg = AArch64::WZR;
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break;
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case AArch64::GPR64RegClassID:
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else if (RC->contains(AArch64::XZR))
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NewReg = AArch64::XZR;
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break;
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else {
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DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
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continue;
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}
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DEBUG(dbgs() << " Replacing with zero register. New:\n ");
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MO.setReg(NewReg);
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MO.setIsDead();
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DEBUG(MI.print(dbgs()));
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++NumDeadDefsReplaced;
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Changed = true;
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@ -145,6 +135,8 @@ bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
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return false;
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TRI = MF.getSubtarget().getRegisterInfo();
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TII = MF.getSubtarget().getInstrInfo();
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MRI = &MF.getRegInfo();
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DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
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Changed = false;
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for (auto &MBB : MF)
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@ -434,6 +434,10 @@ bool AArch64PassConfig::addILPOpts() {
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}
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void AArch64PassConfig::addPreRegAlloc() {
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// Change dead register definitions to refer to the zero register.
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if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
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addPass(createAArch64DeadRegisterDefinitions());
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// Use AdvSIMD scalar instructions whenever profitable.
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if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
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addPass(createAArch64AdvSIMDScalar());
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@ -448,9 +452,6 @@ void AArch64PassConfig::addPostRegAlloc() {
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if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
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addPass(createAArch64RedundantCopyEliminationPass());
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// Change dead register definitions to refer to the zero register.
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if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
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addPass(createAArch64DeadRegisterDefinitions());
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if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
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// Improve performance for some FP/SIMD code for A57.
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addPass(createAArch64A57FPLoadBalancing());
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@ -0,0 +1,91 @@
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; RUN: llc -o - %s | FileCheck %s
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target triple = "aarch64--"
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declare void @begin()
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declare void @end()
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; Test that we use the zero register before regalloc and do not unnecessarily
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; clobber a register with the SUBS (cmp) instruction.
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; CHECK-LABEL: func:
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define void @func(i64* %addr) {
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; We should not see any spills or reloads between begin and end
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; CHECK: bl begin
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; CHECK-NOT: str{{.*}}sp
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; CHECK-NOT: Folded Spill
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; CHECK-NOT: ldr{{.*}}sp
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; CHECK-NOT: Folded Reload
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call void @begin()
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%v0 = load volatile i64, i64* %addr
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%v1 = load volatile i64, i64* %addr
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%v2 = load volatile i64, i64* %addr
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%v3 = load volatile i64, i64* %addr
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%v4 = load volatile i64, i64* %addr
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%v5 = load volatile i64, i64* %addr
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%v6 = load volatile i64, i64* %addr
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%v7 = load volatile i64, i64* %addr
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%v8 = load volatile i64, i64* %addr
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%v9 = load volatile i64, i64* %addr
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%v10 = load volatile i64, i64* %addr
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%v11 = load volatile i64, i64* %addr
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%v12 = load volatile i64, i64* %addr
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%v13 = load volatile i64, i64* %addr
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%v14 = load volatile i64, i64* %addr
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%v15 = load volatile i64, i64* %addr
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%v16 = load volatile i64, i64* %addr
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%v17 = load volatile i64, i64* %addr
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%v18 = load volatile i64, i64* %addr
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%v19 = load volatile i64, i64* %addr
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%v20 = load volatile i64, i64* %addr
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%v21 = load volatile i64, i64* %addr
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%v22 = load volatile i64, i64* %addr
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%v23 = load volatile i64, i64* %addr
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%v24 = load volatile i64, i64* %addr
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%v25 = load volatile i64, i64* %addr
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%v26 = load volatile i64, i64* %addr
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%v27 = load volatile i64, i64* %addr
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%v28 = load volatile i64, i64* %addr
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%v29 = load volatile i64, i64* %addr
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%c = icmp eq i64 %v0, %v1
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br i1 %c, label %if.then, label %if.end
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if.then:
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store volatile i64 %v2, i64* %addr
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br label %if.end
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if.end:
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store volatile i64 %v0, i64* %addr
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store volatile i64 %v1, i64* %addr
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store volatile i64 %v2, i64* %addr
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store volatile i64 %v3, i64* %addr
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store volatile i64 %v4, i64* %addr
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store volatile i64 %v5, i64* %addr
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store volatile i64 %v6, i64* %addr
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store volatile i64 %v7, i64* %addr
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store volatile i64 %v8, i64* %addr
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store volatile i64 %v9, i64* %addr
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store volatile i64 %v10, i64* %addr
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store volatile i64 %v11, i64* %addr
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store volatile i64 %v12, i64* %addr
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store volatile i64 %v13, i64* %addr
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store volatile i64 %v14, i64* %addr
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store volatile i64 %v15, i64* %addr
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store volatile i64 %v16, i64* %addr
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store volatile i64 %v17, i64* %addr
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store volatile i64 %v18, i64* %addr
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store volatile i64 %v19, i64* %addr
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store volatile i64 %v20, i64* %addr
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store volatile i64 %v21, i64* %addr
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store volatile i64 %v22, i64* %addr
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store volatile i64 %v23, i64* %addr
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store volatile i64 %v24, i64* %addr
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store volatile i64 %v25, i64* %addr
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store volatile i64 %v26, i64* %addr
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store volatile i64 %v27, i64* %addr
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store volatile i64 %v28, i64* %addr
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store volatile i64 %v29, i64* %addr
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; CHECK: bl end
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call void @end()
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ret void
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}
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