forked from OSchip/llvm-project
parent
7152dcaf77
commit
3d4cd3d930
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@ -120,6 +120,8 @@ private:
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bool translateMemcpy(const CallInst &CI);
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void getStackGuard(unsigned DstReg);
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bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID);
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/// Translate call instruction.
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@ -382,6 +382,26 @@ bool IRTranslator::translateMemcpy(const CallInst &CI) {
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CallLowering::ArgInfo(0, CI.getType()), Args);
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}
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void IRTranslator::getStackGuard(unsigned DstReg) {
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auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
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MIB.addDef(DstReg);
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auto &MF = MIRBuilder.getMF();
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auto &TLI = *MF.getSubtarget().getTargetLowering();
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Value *Global = TLI.getSDagStackGuard(*MF.getFunction()->getParent());
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if (!Global)
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return;
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MachinePointerInfo MPInfo(Global);
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MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
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auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
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MachineMemOperand::MODereferenceable;
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*MemRefs =
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MF.getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
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DL->getPointerABIAlignment() / 8);
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MIB.setMemRefs(MemRefs, MemRefs + 1);
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}
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bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
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Intrinsic::ID ID) {
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unsigned Op = 0;
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@ -402,6 +422,19 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
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MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
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return true;
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}
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case Intrinsic::stackguard:
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getStackGuard(getOrCreateVReg(CI));
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return true;
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case Intrinsic::stackprotector: {
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// LLT PtrTy{*CI.getArgOperand(0).getType(), *DL};
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// unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
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// getStackGuard(GuardVal);
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// AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
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// unsigned StackSlot = MIRBuilder.buildFrameIndex(FrameReg, FI);
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// MIRBuilder.buildStore(GuardVal, StackSlot);
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return true;
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}
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}
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LLT Ty{*CI.getOperand(0)->getType(), *DL};
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