maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[CSKY] Correct the alignment of FPR register 

The alignment of FPR64 and sFPR64 declared in RegisterClass should be 32 bit.
This commit is contained in:
Zi Xuan Wu 2022-04-08 14:34:21 +08:00
parent 0c789db541
commit 3d4ca8a8c3
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
View File

@ -1721,9 +1721,9 @@ unsigned CSKYAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
if (CSKYMCRegisterClasses[CSKY::FPR32RegClassID].contains(Reg)) {
// As the parser couldn't differentiate an FPR64 from an FPR32, coerce the
// register from FPR32 to FPR64 if necessary.
if (Kind == MCK_FPR64 || Kind == MCK_sFPR64_V) {
if (Kind == MCK_FPR64 || Kind == MCK_sFPR64) {
Op.Reg.RegNum = convertFPR32ToFPR64(Reg);
if (Kind == MCK_sFPR64_V &&
if (Kind == MCK_sFPR64 &&
(Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F15_64))
return Match_InvalidRegOutOfRange;
if (Kind == MCK_FPR64 &&

4
llvm/lib/Target/CSKY/CSKYRegisterInfo.td
View File

@ -193,9 +193,9 @@ def FPR32 : RegisterClass<"CSKY", [f32], 32,
def sFPR32 : RegisterClass<"CSKY", [f32], 32,
(add (sequence "F%u_32", 0, 15))>;
def FPR64 : RegisterClass<"CSKY", [f64], 64,
def FPR64 : RegisterClass<"CSKY", [f64], 32,
(add (sequence "F%u_64", 0, 31))>;
def sFPR64 : RegisterClass<"CSKY", [f64], 64,
def sFPR64 : RegisterClass<"CSKY", [f64], 32,
(add (sequence "F%u_64", 0, 15))>;
def sFPR64_V : RegisterClass<"CSKY", [v2f32], 32, (add sFPR64)>;