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[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.

This commit is contained in:
Craig Topper 2022-06-25 12:19:40 -07:00
parent dc97886fa3
commit 3d37e785c7
28 changed files with 6133 additions and 40930 deletions
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816
llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vcompress_vm_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vcompress.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vcompress_vm_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vcompress.nxv2i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vcompress.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vcompress_vm_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vcompress.nxv4i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vcompress.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vcompress_vm_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vcompress.nxv8i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vcompress.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vcompress_vm_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v10, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vcompress.nxv16i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vcompress.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vcompress_vm_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v12, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vcompress.nxv32i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i1> %2,
i64 %3)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vcompress.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vcompress_vm_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vcompress.vm v8, v16, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vcompress.nxv64i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i1> %2,
i64 %3)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vcompress.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vcompress_vm_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vcompress.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vcompress.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vcompress_vm_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vcompress.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vcompress.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vcompress_vm_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vcompress.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vcompress.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vcompress_vm_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v10, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vcompress.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vcompress.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vcompress_vm_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v12, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vcompress.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vcompress.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vcompress_vm_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
; CHECK-NEXT: vcompress.vm v8, v16, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vcompress.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i1> %2,
i64 %3)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vcompress.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vcompress_vm_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vcompress.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vcompress.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vcompress_vm_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vcompress.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vcompress.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vcompress_vm_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v10, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vcompress.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vcompress.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vcompress_vm_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v12, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vcompress.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vcompress.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vcompress_vm_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: vcompress.vm v8, v16, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vcompress.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vcompress.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vcompress_vm_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vcompress.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vcompress.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vcompress_vm_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v10, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vcompress.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vcompress.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vcompress_vm_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v12, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vcompress.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vcompress.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vcompress_vm_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
; CHECK-NEXT: vcompress.vm v8, v16, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vcompress.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x half> @intrinsic_vcompress_vm_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x half> @intrinsic_vcompress_vm_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x half> @intrinsic_vcompress_vm_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x half> @intrinsic_vcompress_vm_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v10, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x half> @intrinsic_vcompress_vm_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v12, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x half> @intrinsic_vcompress_vm_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
; CHECK-NEXT: vcompress.vm v8, v16, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i1> %2,
i64 %3)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vcompress_vm_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vcompress_vm_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vcompress_vm_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v10, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vcompress.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vcompress_vm_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v12, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vcompress.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vcompress.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vcompress_vm_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: vcompress.vm v8, v16, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vcompress.nxv16f32(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vcompress.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vcompress_vm_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vcompress.vm v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vcompress.nxv1f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vcompress.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vcompress_vm_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vcompress.vm v8, v10, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vcompress.nxv2f64(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vcompress.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vcompress_vm_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vcompress.vm v8, v12, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vcompress.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vcompress.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vcompress_vm_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
; CHECK-NEXT: vcompress.vm v8, v16, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vcompress.nxv8f64(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x double> %a
}

228
llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll → llvm/test/CodeGen/RISCV/rvv/vcompress.ll
View File

@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
i32);
iXLen);
define <vscale x 1 x i8> @intrinsic_vcompress_vm_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
define <vscale x 1 x i8> @intrinsic_vcompress_vm_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 1 x i8> %a
}
@ -27,9 +29,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vcompress.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
i32);
iXLen);
define <vscale x 2 x i8> @intrinsic_vcompress_vm_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
define <vscale x 2 x i8> @intrinsic_vcompress_vm_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
@ -40,7 +42,7 @@ entry:
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 2 x i8> %a
}
@ -49,9 +51,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vcompress.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
i32);
iXLen);
define <vscale x 4 x i8> @intrinsic_vcompress_vm_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
define <vscale x 4 x i8> @intrinsic_vcompress_vm_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
@ -62,7 +64,7 @@ entry:
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 4 x i8> %a
}
@ -71,9 +73,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vcompress.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
i32);
iXLen);
define <vscale x 8 x i8> @intrinsic_vcompress_vm_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
define <vscale x 8 x i8> @intrinsic_vcompress_vm_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
@ -84,7 +86,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 8 x i8> %a
}
@ -93,9 +95,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vcompress.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
i32);
iXLen);
define <vscale x 16 x i8> @intrinsic_vcompress_vm_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
define <vscale x 16 x i8> @intrinsic_vcompress_vm_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
@ -106,7 +108,7 @@ entry:
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 16 x i8> %a
}
@ -115,9 +117,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vcompress.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
i32);
iXLen);
define <vscale x 32 x i8> @intrinsic_vcompress_vm_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
define <vscale x 32 x i8> @intrinsic_vcompress_vm_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
@ -128,7 +130,7 @@ entry:
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 32 x i8> %a
}
@ -137,9 +139,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vcompress.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
i32);
iXLen);
define <vscale x 64 x i8> @intrinsic_vcompress_vm_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
define <vscale x 64 x i8> @intrinsic_vcompress_vm_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
@ -150,7 +152,7 @@ entry:
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 64 x i8> %a
}
@ -159,9 +161,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vcompress.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i32);
iXLen);
define <vscale x 1 x i16> @intrinsic_vcompress_vm_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
define <vscale x 1 x i16> @intrinsic_vcompress_vm_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
@ -172,7 +174,7 @@ entry:
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 1 x i16> %a
}
@ -181,9 +183,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vcompress.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i32);
iXLen);
define <vscale x 2 x i16> @intrinsic_vcompress_vm_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
define <vscale x 2 x i16> @intrinsic_vcompress_vm_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
@ -194,7 +196,7 @@ entry:
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 2 x i16> %a
}
@ -203,9 +205,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vcompress.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i32);
iXLen);
define <vscale x 4 x i16> @intrinsic_vcompress_vm_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
define <vscale x 4 x i16> @intrinsic_vcompress_vm_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
@ -216,7 +218,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 4 x i16> %a
}
@ -225,9 +227,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vcompress.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i32);
iXLen);
define <vscale x 8 x i16> @intrinsic_vcompress_vm_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
define <vscale x 8 x i16> @intrinsic_vcompress_vm_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
@ -238,7 +240,7 @@ entry:
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 8 x i16> %a
}
@ -247,9 +249,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vcompress.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i32);
iXLen);
define <vscale x 16 x i16> @intrinsic_vcompress_vm_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
define <vscale x 16 x i16> @intrinsic_vcompress_vm_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
@ -260,7 +262,7 @@ entry:
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 16 x i16> %a
}
@ -269,9 +271,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vcompress.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i32);
iXLen);
define <vscale x 32 x i16> @intrinsic_vcompress_vm_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
define <vscale x 32 x i16> @intrinsic_vcompress_vm_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
@ -282,7 +284,7 @@ entry:
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 32 x i16> %a
}
@ -291,9 +293,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vcompress.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i32);
iXLen);
define <vscale x 1 x i32> @intrinsic_vcompress_vm_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
define <vscale x 1 x i32> @intrinsic_vcompress_vm_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
@ -304,7 +306,7 @@ entry:
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 1 x i32> %a
}
@ -313,9 +315,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vcompress.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i32);
iXLen);
define <vscale x 2 x i32> @intrinsic_vcompress_vm_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
define <vscale x 2 x i32> @intrinsic_vcompress_vm_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
@ -326,7 +328,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 2 x i32> %a
}
@ -335,9 +337,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vcompress.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i32);
iXLen);
define <vscale x 4 x i32> @intrinsic_vcompress_vm_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
define <vscale x 4 x i32> @intrinsic_vcompress_vm_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
@ -348,7 +350,7 @@ entry:
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 4 x i32> %a
}
@ -357,9 +359,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vcompress.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i32);
iXLen);
define <vscale x 8 x i32> @intrinsic_vcompress_vm_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
define <vscale x 8 x i32> @intrinsic_vcompress_vm_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
@ -370,7 +372,7 @@ entry:
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 8 x i32> %a
}
@ -379,9 +381,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vcompress.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
i32);
iXLen);
define <vscale x 16 x i32> @intrinsic_vcompress_vm_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
define <vscale x 16 x i32> @intrinsic_vcompress_vm_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
@ -392,7 +394,7 @@ entry:
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 16 x i32> %a
}
@ -401,9 +403,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vcompress.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i32);
iXLen);
define <vscale x 1 x i64> @intrinsic_vcompress_vm_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
define <vscale x 1 x i64> @intrinsic_vcompress_vm_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
@ -414,7 +416,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 1 x i64> %a
}
@ -423,9 +425,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vcompress.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i32);
iXLen);
define <vscale x 2 x i64> @intrinsic_vcompress_vm_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
define <vscale x 2 x i64> @intrinsic_vcompress_vm_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
@ -436,7 +438,7 @@ entry:
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 2 x i64> %a
}
@ -445,9 +447,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vcompress.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i32);
iXLen);
define <vscale x 4 x i64> @intrinsic_vcompress_vm_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
define <vscale x 4 x i64> @intrinsic_vcompress_vm_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
@ -458,7 +460,7 @@ entry:
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 4 x i64> %a
}
@ -467,9 +469,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vcompress.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i32);
iXLen);
define <vscale x 8 x i64> @intrinsic_vcompress_vm_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
define <vscale x 8 x i64> @intrinsic_vcompress_vm_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
@ -480,7 +482,7 @@ entry:
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 8 x i64> %a
}
@ -489,9 +491,9 @@ declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i32);
iXLen);
define <vscale x 1 x half> @intrinsic_vcompress_vm_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
define <vscale x 1 x half> @intrinsic_vcompress_vm_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
@ -502,7 +504,7 @@ entry:
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 1 x half> %a
}
@ -511,9 +513,9 @@ declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i32);
iXLen);
define <vscale x 2 x half> @intrinsic_vcompress_vm_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
define <vscale x 2 x half> @intrinsic_vcompress_vm_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
@ -524,7 +526,7 @@ entry:
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 2 x half> %a
}
@ -533,9 +535,9 @@ declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i32);
iXLen);
define <vscale x 4 x half> @intrinsic_vcompress_vm_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
define <vscale x 4 x half> @intrinsic_vcompress_vm_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
@ -546,7 +548,7 @@ entry:
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 4 x half> %a
}
@ -555,9 +557,9 @@ declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i32);
iXLen);
define <vscale x 8 x half> @intrinsic_vcompress_vm_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
define <vscale x 8 x half> @intrinsic_vcompress_vm_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
@ -568,7 +570,7 @@ entry:
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 8 x half> %a
}
@ -577,9 +579,9 @@ declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i32);
iXLen);
define <vscale x 16 x half> @intrinsic_vcompress_vm_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
define <vscale x 16 x half> @intrinsic_vcompress_vm_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
@ -590,7 +592,7 @@ entry:
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 16 x half> %a
}
@ -599,9 +601,9 @@ declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i1>,
i32);
iXLen);
define <vscale x 32 x half> @intrinsic_vcompress_vm_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
define <vscale x 32 x half> @intrinsic_vcompress_vm_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
@ -612,7 +614,7 @@ entry:
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 32 x half> %a
}
@ -621,9 +623,9 @@ declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i32);
iXLen);
define <vscale x 1 x float> @intrinsic_vcompress_vm_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
define <vscale x 1 x float> @intrinsic_vcompress_vm_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
@ -634,7 +636,7 @@ entry:
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 1 x float> %a
}
@ -643,9 +645,9 @@ declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i32);
iXLen);
define <vscale x 2 x float> @intrinsic_vcompress_vm_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
define <vscale x 2 x float> @intrinsic_vcompress_vm_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
@ -656,7 +658,7 @@ entry:
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 2 x float> %a
}
@ -665,9 +667,9 @@ declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i32);
iXLen);
define <vscale x 4 x float> @intrinsic_vcompress_vm_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
define <vscale x 4 x float> @intrinsic_vcompress_vm_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
@ -678,7 +680,7 @@ entry:
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 4 x float> %a
}
@ -687,9 +689,9 @@ declare <vscale x 8 x float> @llvm.riscv.vcompress.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i32);
iXLen);
define <vscale x 8 x float> @intrinsic_vcompress_vm_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
define <vscale x 8 x float> @intrinsic_vcompress_vm_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
@ -700,7 +702,7 @@ entry:
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 8 x float> %a
}
@ -709,9 +711,9 @@ declare <vscale x 16 x float> @llvm.riscv.vcompress.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i1>,
i32);
iXLen);
define <vscale x 16 x float> @intrinsic_vcompress_vm_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
define <vscale x 16 x float> @intrinsic_vcompress_vm_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
@ -722,7 +724,7 @@ entry:
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 16 x float> %a
}
@ -731,9 +733,9 @@ declare <vscale x 1 x double> @llvm.riscv.vcompress.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
i32);
iXLen);
define <vscale x 1 x double> @intrinsic_vcompress_vm_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
define <vscale x 1 x double> @intrinsic_vcompress_vm_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
@ -744,7 +746,7 @@ entry:
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
<vscale x 1 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 1 x double> %a
}
@ -753,9 +755,9 @@ declare <vscale x 2 x double> @llvm.riscv.vcompress.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
i32);
iXLen);
define <vscale x 2 x double> @intrinsic_vcompress_vm_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
define <vscale x 2 x double> @intrinsic_vcompress_vm_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
@ -766,7 +768,7 @@ entry:
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
<vscale x 2 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 2 x double> %a
}
@ -775,9 +777,9 @@ declare <vscale x 4 x double> @llvm.riscv.vcompress.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
i32);
iXLen);
define <vscale x 4 x double> @intrinsic_vcompress_vm_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
define <vscale x 4 x double> @intrinsic_vcompress_vm_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
@ -788,7 +790,7 @@ entry:
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
<vscale x 4 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 4 x double> %a
}
@ -797,9 +799,9 @@ declare <vscale x 8 x double> @llvm.riscv.vcompress.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i1>,
i32);
iXLen);
define <vscale x 8 x double> @intrinsic_vcompress_vm_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
define <vscale x 8 x double> @intrinsic_vcompress_vm_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
@ -810,7 +812,7 @@ entry:
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
<vscale x 8 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 8 x double> %a
}

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