forked from OSchip/llvm-project
AMDGPU: waitcnt operand fixes
Summary: Allow lgkmcnt up to 0xF (hardware allows that). Fix mask for ExpCnt in AMDGPUInstPrinter. Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16314 Patch by: Nikolay Haustov llvm-svn: 259059
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e5cadbbcdd
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3d2c852958
llvm
lib/Target/AMDGPU
test/MC/AMDGPU
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@ -1516,7 +1516,7 @@ bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
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CntMask = 0x7;
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CntShift = 4;
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} else if (CntName == "lgkmcnt") {
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CntMask = 0x7;
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CntMask = 0xf;
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CntShift = 8;
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} else {
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return true;
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@ -1532,8 +1532,8 @@ AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
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// Disable all counters by default.
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// vmcnt [3:0]
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// expcnt [6:4]
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// lgkmcnt [10:8]
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int64_t CntVal = 0x77f;
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// lgkmcnt [11:8]
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int64_t CntVal = 0xf7f;
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SMLoc S = Parser.getTok().getLoc();
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switch(getLexer().getKind()) {
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@ -616,12 +616,9 @@ void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
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void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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// Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
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// SIInsertWaits.cpp bits usage does not match ISA docs description but it
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// works so it might be a misprint in docs.
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unsigned SImm16 = MI->getOperand(OpNo).getImm();
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unsigned Vmcnt = SImm16 & 0xF;
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unsigned Expcnt = (SImm16 >> 4) & 0xF;
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unsigned Expcnt = (SImm16 >> 4) & 0x7;
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unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
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bool NeedSpace = false;
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@ -638,7 +635,7 @@ void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
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NeedSpace = true;
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}
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if (Lgkmcnt != 0x7) {
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if (Lgkmcnt != 0xF) {
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if (NeedSpace)
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O << ' ';
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O << "lgkmcnt(" << Lgkmcnt << ')';
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@ -138,7 +138,7 @@ public:
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char SIInsertWaits::ID = 0;
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const Counters SIInsertWaits::WaitCounts = { { 15, 7, 7 } };
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const Counters SIInsertWaits::WaitCounts = { { 15, 7, 15 } };
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const Counters SIInsertWaits::ZeroCounts = { { 0, 0, 0 } };
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FunctionPass *llvm::createSIInsertWaits(TargetMachine &tm) {
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@ -379,7 +379,7 @@ bool SIInsertWaits::insertWait(MachineBasicBlock &MBB,
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BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
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.addImm((Counts.Named.VM & 0xF) |
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((Counts.Named.EXP & 0x7) << 4) |
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((Counts.Named.LGKM & 0x7) << 8));
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((Counts.Named.LGKM & 0xF) << 8));
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LastOpcodeType = OTHER;
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LastInstWritesM0 = false;
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@ -40,16 +40,22 @@ s_nop 0xffff // CHECK: s_nop 0xffff ; encoding: [0xff,0xff,0x80,0xbf]
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// CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
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s_waitcnt vmcnt(1)
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// CHECK: s_waitcnt vmcnt(1) ; encoding: [0x71,0x07,0x8c,0xbf]
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// CHECK: s_waitcnt vmcnt(1) ; encoding: [0x71,0x0f,0x8c,0xbf]
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s_waitcnt vmcnt(9)
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// CHECK: s_waitcnt vmcnt(9) ; encoding: [0x79,0x0f,0x8c,0xbf]
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s_waitcnt expcnt(2)
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// CHECK: s_waitcnt expcnt(2) ; encoding: [0x2f,0x07,0x8c,0xbf]
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// CHECK: s_waitcnt expcnt(2) ; encoding: [0x2f,0x0f,0x8c,0xbf]
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s_waitcnt lgkmcnt(3)
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// CHECK: s_waitcnt lgkmcnt(3) ; encoding: [0x7f,0x03,0x8c,0xbf]
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s_waitcnt lgkmcnt(9)
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// CHECK: s_waitcnt lgkmcnt(9) ; encoding: [0x7f,0x09,0x8c,0xbf]
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s_waitcnt vmcnt(0), expcnt(0)
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// CHECK: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x07,0x8c,0xbf]
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// CHECK: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x0f,0x8c,0xbf]
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s_sethalt 9 // CHECK: s_sethalt 9 ; encoding: [0x09,0x00,0x8d,0xbf]
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