forked from OSchip/llvm-project
[AArch64][GlobalISel] Allow vector store legalization into 128-bit-wide types
We are allowed to store 128-bit-wide values using the q registers on AArch64. GlobalISel was clamping the number of elements in vector stores into 64 bits instead. This results in some poor codegen like below: https://godbolt.org/z/E56dq8 ``` ; SDAG uses a stp + q registers in both cases here. define void @float(<16 x float> %val, <16 x float>* %ptr) { store <16 x float> %val, <16 x float>* %ptr ret void } define void @double(<8 x double> %val, <8 x double>* %ptr) { store <8 x double> %val, <8 x double>* %ptr ret void } ``` This adds similar legalization for vector stores with s8 and s16 elements. Differential Revision: https://reviews.llvm.org/D95107
This commit is contained in:
Jessica Paquette
parent
fb12df4a8e
commit
3d25fdc5c2
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@ -319,8 +319,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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return Query.Types[0].isScalar() &&
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Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits;
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})
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.clampMaxNumElements(0, s32, 2)
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.clampMaxNumElements(0, s64, 1)
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// Maximum: sN * k = 128
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.clampMaxNumElements(0, s8, 16)
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.clampMaxNumElements(0, s16, 8)
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.clampMaxNumElements(0, s32, 4)
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.clampMaxNumElements(0, s64, 2)
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.customIf(IsPtrVecPred);
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// Constants
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@ -19,18 +19,10 @@ body: |
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; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
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; CHECK: [[FPEXT:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
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; CHECK: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>)
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; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT]](<2 x s64>)
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; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT1]](<2 x s64>)
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; CHECK: G_STORE [[UV2]](s64), [[COPY1]](p0) :: (store 8, align 32)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
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; CHECK: G_STORE [[FPEXT]](<2 x s64>), [[COPY1]](p0) :: (store 16, align 32)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s64)
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; CHECK: G_STORE [[UV3]](s64), [[PTR_ADD]](p0) :: (store 8 + 8)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
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; CHECK: G_STORE [[UV4]](s64), [[PTR_ADD1]](p0) :: (store 8 + 16, align 16)
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
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; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64)
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; CHECK: G_STORE [[UV5]](s64), [[PTR_ADD2]](p0) :: (store 8 + 24)
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; CHECK: G_STORE [[FPEXT1]](<2 x s64>), [[PTR_ADD]](p0) :: (store 16 + 16)
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; CHECK: RET_ReallyLR
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%0:_(<4 x s32>) = COPY $q0
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%1:_(p0) = COPY $x0
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@ -115,16 +115,12 @@ body: |
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; CHECK: [[FPTRUNC2:%[0-9]+]]:_(<2 x s32>) = G_FPTRUNC [[COPY2]](<2 x s64>)
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; CHECK: [[FPTRUNC3:%[0-9]+]]:_(<2 x s32>) = G_FPTRUNC [[COPY3]](<2 x s64>)
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; CHECK: [[COPY5:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: G_STORE [[FPTRUNC]](<2 x s32>), [[COPY5]](p0) :: (store 8, align 32)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[FPTRUNC]](<2 x s32>), [[FPTRUNC1]](<2 x s32>)
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; CHECK: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[FPTRUNC2]](<2 x s32>), [[FPTRUNC3]](<2 x s32>)
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; CHECK: G_STORE [[CONCAT_VECTORS]](<4 x s32>), [[COPY5]](p0) :: (store 16, align 32)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY5]], [[C]](s64)
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; CHECK: G_STORE [[FPTRUNC1]](<2 x s32>), [[PTR_ADD]](p0) :: (store 8 + 8)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY5]], [[C1]](s64)
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; CHECK: G_STORE [[FPTRUNC2]](<2 x s32>), [[PTR_ADD1]](p0) :: (store 8 + 16, align 16)
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
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; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY5]], [[C2]](s64)
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; CHECK: G_STORE [[FPTRUNC3]](<2 x s32>), [[PTR_ADD2]](p0) :: (store 8 + 24)
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; CHECK: G_STORE [[CONCAT_VECTORS1]](<4 x s32>), [[PTR_ADD]](p0) :: (store 16 + 16)
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; CHECK: RET_ReallyLR
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%2:_(<2 x s64>) = COPY $q0
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%3:_(<2 x s64>) = COPY $q1
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@ -302,3 +302,96 @@ body: |
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G_STORE %1(<8 x s8>), %0(p0) :: (store 8)
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RET_ReallyLR
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...
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---
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name: store_32xs8
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: store_32xs8
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; CHECK: liveins: $x0
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; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
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; CHECK: %ptr:_(p0) = COPY $x0
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
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; CHECK: G_STORE [[BUILD_VECTOR]](<16 x s8>), %ptr(p0) :: (store 16, align 32)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
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; CHECK: G_STORE [[BUILD_VECTOR1]](<16 x s8>), [[PTR_ADD]](p0) :: (store 16 + 16)
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; CHECK: RET_ReallyLR
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%val:_(<32 x s8>) = G_IMPLICIT_DEF
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%ptr:_(p0) = COPY $x0
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G_STORE %val(<32 x s8>), %ptr(p0) :: (store 32)
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RET_ReallyLR
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...
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---
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name: store_16xs16
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: store_16xs16
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; CHECK: liveins: $x0
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; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
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; CHECK: %ptr:_(p0) = COPY $x0
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
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; CHECK: G_STORE [[BUILD_VECTOR]](<8 x s16>), %ptr(p0) :: (store 16, align 32)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
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; CHECK: G_STORE [[BUILD_VECTOR1]](<8 x s16>), [[PTR_ADD]](p0) :: (store 16 + 16)
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; CHECK: RET_ReallyLR
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%val:_(<16 x s16>) = G_IMPLICIT_DEF
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%ptr:_(p0) = COPY $x0
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G_STORE %val(<16 x s16>), %ptr(p0) :: (store 32)
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RET_ReallyLR
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...
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---
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name: store_8xs32
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: store_8xs32
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; CHECK: liveins: $x0
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; CHECK: %ptr:_(p0) = COPY $x0
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
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; CHECK: G_STORE [[BUILD_VECTOR]](<4 x s32>), %ptr(p0) :: (store 16, align 32)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
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; CHECK: G_STORE [[BUILD_VECTOR1]](<4 x s32>), [[PTR_ADD]](p0) :: (store 16 + 16)
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; CHECK: RET_ReallyLR
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%val:_(<8 x s32>) = G_IMPLICIT_DEF
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%ptr:_(p0) = COPY $x0
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G_STORE %val(<8 x s32>), %ptr(p0) :: (store 32)
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RET_ReallyLR
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...
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---
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name: store_4xs64
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: store_4xs64
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; CHECK: liveins: $x0
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; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
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; CHECK: %ptr:_(p0) = COPY $x0
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; CHECK: G_STORE [[DEF]](<2 x s64>), %ptr(p0) :: (store 16, align 32)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
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; CHECK: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store 16 + 16)
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; CHECK: RET_ReallyLR
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%val:_(<4 x s64>) = G_IMPLICIT_DEF
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%ptr:_(p0) = COPY $x0
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G_STORE %val(<4 x s64>), %ptr(p0) :: (store 32)
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RET_ReallyLR
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