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[AArch64] Add v8.5-a Memory Tagging STZGM instruction 

This instruction writes a block of allocation tags
and stores zero to the associated data locations.

It differs from STGM by 1 bit and has the same
arguments.

The specification can be found here:
https://developer.arm.com/docs/ddi0596/c

Differential Revision: https://reviews.llvm.org/D60065

llvm-svn: 357397
This commit is contained in:
David Spickett 2019-04-01 14:56:37 +00:00
parent 44668ae7c7
commit 3d233d5d4d
4 changed files with 53 additions and 0 deletions
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4
llvm/lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -1261,6 +1261,10 @@ def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
(outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;
def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]",
(outs), (ins GPR64:$Rt, GPR64sp:$Rn)> {
let Inst{23} = 0;
}
defm STG : MemTagStore<0b00, "stg">;
defm STZG : MemTagStore<0b01, "stzg">;

23
llvm/test/MC/AArch64/armv8.5a-mte-error.s
View File

@ -858,3 +858,26 @@ stgm x0, [#1]
// CHECK-NEXT: stgm #1, [x1]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stgm x0, [#1]
stzgm
stzgm x0
stzgm sp, [x0]
stzgm w0, [x0]
stzgm x0, [w0]
stzgm #1, [x1]
stzgm x0, [#1]
// CHECK: too few operands for instruction
// CHECK-NEXT: stzgm
// CHECK: too few operands for instruction
// CHECK-NEXT: stzgm x0
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm sp, [x0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm w0, [x0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm x0, [w0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm #1, [x1]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm x0, [#1]

14
llvm/test/MC/AArch64/armv8.5a-mte.s
View File

@ -542,6 +542,7 @@ ldgm xzr, [x2]
// CHECK: ldgm x1, [sp] // encoding: [0xe1,0x03,0xe0,0xd9]
// CHECK: ldgm xzr, [x2] // encoding: [0x5f,0x00,0xe0,0xd9]
// NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte
@ -555,3 +556,16 @@ stgm xzr, [x2]
// NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte
stzgm x0, [x1]
stzgm x1, [sp]
stzgm xzr, [x2]
// CHECK: stzgm x0, [x1] // encoding: [0x20,0x00,0x20,0xd9]
// CHECK: stzgm x1, [sp] // encoding: [0xe1,0x03,0x20,0xd9]
// CHECK: stzgm xzr, [x2] // encoding: [0x5f,0x00,0x20,0xd9]
// NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte

12
llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
View File

@ -407,6 +407,9 @@
[0x20,0x00,0xa0,0xd9]
[0xe1,0x03,0xa0,0xd9]
[0x5f,0x00,0xa0,0xd9]
[0x20,0x00,0x20,0xd9]
[0xe1,0x03,0x20,0xd9]
[0x5f,0x00,0x20,0xd9]
# CHECK: ldgm x0, [x1]
# CHECK: ldgm x1, [sp]
@ -414,6 +417,9 @@
# CHECK: stgm x0, [x1]
# CHECK: stgm x1, [sp]
# CHECK: stgm xzr, [x2]
# CHECK: stzgm x0, [x1]
# CHECK: stzgm x1, [sp]
# CHECK: stzgm xzr, [x2]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x20,0x00,0xe0,0xd9]
@ -427,6 +433,12 @@
# NOMTE-NEXT: [0xe1,0x03,0xa0,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0x00,0xa0,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x20,0x00,0x20,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xe1,0x03,0x20,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0x00,0x20,0xd9]
[0x60,0x76,0x08,0xd5]
[0x81,0x76,0x08,0xd5]