forked from OSchip/llvm-project
[NFC][Codegen][X86] Autogenerate check lines in avx.ll test
This commit is contained in:
Roman Lebedev
parent
0ba8595287
commit
3d157fb627
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@ -1,26 +1,41 @@
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; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx | FileCheck %s --check-prefixes=X32,CHECK
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx | FileCheck %s --check-prefixes=CHECK,X32
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s --check-prefixes=CHECK,X64
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define <4 x i32> @blendvb_fallback_v4i32(<4 x i1> %mask, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @blendvb_fallback_v4i32
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; CHECK: vblendvps
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; CHECK: ret
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; CHECK-LABEL: blendvb_fallback_v4i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
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; CHECK-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%ret = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %ret
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}
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define <8 x i32> @blendvb_fallback_v8i32(<8 x i1> %mask, <8 x i32> %x, <8 x i32> %y) {
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; CHECK-LABEL: @blendvb_fallback_v8i32
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; CHECK: vblendvps
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; CHECK: ret
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; CHECK-LABEL: blendvb_fallback_v8i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
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; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
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; CHECK-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
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; CHECK-NEXT: ret{{[l|q]}}
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%ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
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ret <8 x i32> %ret
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}
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define <8 x float> @blendvb_fallback_v8f32(<8 x i1> %mask, <8 x float> %x, <8 x float> %y) {
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; CHECK-LABEL: @blendvb_fallback_v8f32
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; CHECK: vblendvps
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; CHECK: ret
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; CHECK-LABEL: blendvb_fallback_v8f32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
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; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
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; CHECK-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
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; CHECK-NEXT: ret{{[l|q]}}
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%ret = select <8 x i1> %mask, <8 x float> %x, <8 x float> %y
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ret <8 x float> %ret
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}
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@ -28,12 +43,17 @@ define <8 x float> @blendvb_fallback_v8f32(<8 x i1> %mask, <8 x float> %x, <8 x
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
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; CHECK-LABEL: insertps_from_vector_load:
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; On X32, account for the argument's move to registers
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; X32: movl 4(%esp), %eax
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; CHECK-NOT: mov
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; CHECK: vinsertps $48, (%{{...}}), {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; CHECK-NEXT: ret
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; X32-LABEL: insertps_from_vector_load:
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; X32: ## %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_from_vector_load:
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; X64: ## %bb.0:
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; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; X64-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %pb, align 16
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%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
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ret <4 x float> %2
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@ -41,27 +61,39 @@ define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocap
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;; Use a non-zero CountS for insertps
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define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
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; CHECK-LABEL: insertps_from_vector_load_offset:
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; On X32, account for the argument's move to registers
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; X32: movl 4(%esp), %eax
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; CHECK-NOT: mov
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;; Try to match a bit more of the instr, since we need the load's offset.
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; CHECK: vinsertps $32, 4(%{{...}}), {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
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; CHECK-NEXT: ret
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; X32-LABEL: insertps_from_vector_load_offset:
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; X32: ## %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_from_vector_load_offset:
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; X64: ## %bb.0:
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; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
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; X64-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %pb, align 16
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%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
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ret <4 x float> %2
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}
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define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) {
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; CHECK-LABEL: insertps_from_vector_load_offset_2:
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; On X32, account for the argument's move to registers
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; X32: movl 4(%esp), %eax
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; X32: movl 8(%esp), %ecx
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; CHECK-NOT: mov
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;; Try to match a bit more of the instr, since we need the load's offset.
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; CHECK: vinsertps $0, 12(%{{...}},%{{...}}), {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
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; CHECK-NEXT: ret
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; X32-LABEL: insertps_from_vector_load_offset_2:
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; X32: ## %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: shll $4, %ecx
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; X32-NEXT: vinsertps {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_from_vector_load_offset_2:
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; X64: ## %bb.0:
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; X64-NEXT: shlq $4, %rsi
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; X64-NEXT: vinsertps {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
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; X64-NEXT: retq
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%1 = getelementptr inbounds <4 x float>, <4 x float>* %pb, i64 %index
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%2 = load <4 x float>, <4 x float>* %1, align 16
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%3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
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@ -69,13 +101,18 @@ define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x floa
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}
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define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocapture readonly %fb, i64 %index) {
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; CHECK-LABEL: insertps_from_broadcast_loadf32:
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; On X32, account for the arguments' move to registers
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; X32: movl 8(%esp), %eax
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; X32: movl 4(%esp), %ecx
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK-NEXT: ret
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; X32-LABEL: insertps_from_broadcast_loadf32:
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; X32: ## %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_from_broadcast_loadf32:
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; X64: ## %bb.0:
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; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; X64-NEXT: retq
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%1 = getelementptr inbounds float, float* %fb, i64 %index
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%2 = load float, float* %1, align 4
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%3 = insertelement <4 x float> undef, float %2, i32 0
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@ -87,12 +124,17 @@ define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocap
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}
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define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float>* nocapture readonly %b) {
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; CHECK-LABEL: insertps_from_broadcast_loadv4f32:
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; On X32, account for the arguments' move to registers
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; X32: movl 4(%esp), %{{...}}
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK-NEXT: ret
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; X32-LABEL: insertps_from_broadcast_loadv4f32:
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; X32: ## %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_from_broadcast_loadv4f32:
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; X64: ## %bb.0:
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; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; X64-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %b, align 4
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%2 = extractelement <4 x float> %1, i32 0
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%3 = insertelement <4 x float> undef, float %2, i32 0
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@ -105,20 +147,32 @@ define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float
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;; FIXME: We're emitting an extraneous pshufd/vbroadcast.
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define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* nocapture readonly %fb, i64 %index) {
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; CHECK-LABEL: insertps_from_broadcast_multiple_use:
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; On X32, account for the arguments' move to registers
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; X32: movl 8(%esp), %eax
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; X32: movl 4(%esp), %ecx
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; CHECK: vbroadcastss
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK: insertps $48
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; CHECK: vaddps
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; CHECK: insertps $48
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; CHECK: insertps $48
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; CHECK: vaddps
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; CHECK: vaddps
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; CHECK-NEXT: ret
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; X32-LABEL: insertps_from_broadcast_multiple_use:
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; X32: ## %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vbroadcastss (%ecx,%eax,4), %xmm4
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; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
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; X32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
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; X32-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; X32-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm4[0]
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; X32-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0,1,2],xmm4[0]
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; X32-NEXT: vaddps %xmm2, %xmm1, %xmm1
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; X32-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_from_broadcast_multiple_use:
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; X64: ## %bb.0:
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; X64-NEXT: vbroadcastss (%rdi,%rsi,4), %xmm4
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; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
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; X64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
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; X64-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; X64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm4[0]
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; X64-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0,1,2],xmm4[0]
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; X64-NEXT: vaddps %xmm2, %xmm1, %xmm1
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; X64-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; X64-NEXT: retq
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%1 = getelementptr inbounds float, float* %fb, i64 %index
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%2 = load float, float* %1, align 4
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%3 = insertelement <4 x float> undef, float %2, i32 0
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