From 3d134ebb737f773f6c4f79ce35333ba059d5e6f6 Mon Sep 17 00:00:00 2001
From: Logan Chien <tzuhsiang.chien@gmail.com>
Date: Tue, 16 Apr 2013 14:02:30 +0000
Subject: [PATCH] Fix build failure introduced in 179591 when assertions are
 disabled.

llvm-svn: 179593
---
 llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index f17dcdf6ab2f..52d92375aaf1 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -428,7 +428,9 @@ void ARMELFStreamer::EmitSetFP(unsigned NewFPReg,
   const MCRegisterInfo &MRI = getContext().getRegisterInfo();
 
   uint16_t NewFPRegEncVal = MRI.getEncodingValue(NewFPReg);
+#ifndef NDEBUG
   uint16_t NewSPRegEncVal = MRI.getEncodingValue(NewSPReg);
+#endif
 
   assert((NewSPReg == ARM::SP || NewSPRegEncVal == FPReg) &&
          "the operand of .setfp directive should be either $sp or $fp");
@@ -446,7 +448,9 @@ void ARMELFStreamer::EmitRegSave(const SmallVectorImpl<unsigned> &RegList,
                                  bool IsVector) {
   const MCRegisterInfo &MRI = getContext().getRegisterInfo();
 
+#ifndef NDEBUG
   unsigned Max = IsVector ? 32 : 16;
+#endif
   uint32_t &RegMask = IsVector ? VFPRegSave : RegSave;
 
   for (size_t i = 0; i < RegList.size(); ++i) {