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[ARM] Reorder some logic 

Re-order some checks in ValidateMVEInst.
This commit is contained in:
Sam Parker 2020-09-16 13:38:36 +01:00
parent 6a23668e78
commit 3ce9ec0cfa
1 changed files with 18 additions and 16 deletions
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34
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
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@ -854,6 +854,24 @@ bool LowOverheadLoop::ValidateMVEInst(MachineInstr* MI) {
if (CannotTailPredicate)
return false;
const MCInstrDesc &MCID = MI->getDesc();
uint64_t Flags = MCID.TSFlags;
if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
return true;
if (MI->getOpcode() == ARM::MVE_VPSEL ||
MI->getOpcode() == ARM::MVE_VPNOT) {
// TODO: Allow VPSEL and VPNOT, we currently cannot because:
// 1) It will use the VPR as a predicate operand, but doesn't have to be
// instead a VPT block, which means we can assert while building up
// the VPT block because we don't find another VPT or VPST to being a new
// one.
// 2) VPSEL still requires a VPR operand even after tail predicating,
// which means we can't remove it unless there is another
// instruction, such as vcmp, that can provide the VPR def.
return false;
}
if (isVCTP(MI)) {
// If we find another VCTP, check whether it uses the same value as the main VCTP.
// If it does, store it in the SecondaryVCTPs set, else refuse it.
@ -881,22 +899,10 @@ bool LowOverheadLoop::ValidateMVEInst(MachineInstr* MI) {
VPTBlocks.emplace_back(MI, CurrentPredicate);
CurrentBlock = &VPTBlocks.back();
return true;
} else if (MI->getOpcode() == ARM::MVE_VPSEL ||
MI->getOpcode() == ARM::MVE_VPNOT) {
// TODO: Allow VPSEL and VPNOT, we currently cannot because:
// 1) It will use the VPR as a predicate operand, but doesn't have to be
// instead a VPT block, which means we can assert while building up
// the VPT block because we don't find another VPT or VPST to being a new
// one.
// 2) VPSEL still requires a VPR operand even after tail predicating,
// which means we can't remove it unless there is another
// instruction, such as vcmp, that can provide the VPR def.
return false;
}
bool IsUse = false;
bool IsDef = false;
const MCInstrDesc &MCID = MI->getDesc();
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || MO.getReg() != ARM::VPR)
@ -932,10 +938,6 @@ bool LowOverheadLoop::ValidateMVEInst(MachineInstr* MI) {
return false;
}
uint64_t Flags = MCID.TSFlags;
if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
return true;
// If we find an instruction that has been marked as not valid for tail
// predication, only allow the instruction if it's contained within a valid
// VPT block.