forked from OSchip/llvm-project
Revert "[CGP] Split some critical edges coming out of indirect branches"
This reverts commit r296149 as it leads to crashes when compiling for PPC. llvm-svn: 296295
This commit is contained in:
parent
49a0aac1aa
commit
3ca4525612
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@ -15,12 +15,10 @@
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/BlockFrequencyInfo.h"
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#include "llvm/Analysis/BranchProbabilityInfo.h"
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#include "llvm/Analysis/CFG.h"
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#include "llvm/Analysis/InstructionSimplify.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/ProfileSummaryInfo.h"
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@ -55,10 +53,8 @@
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#include "llvm/Transforms/Utils/BasicBlockUtils.h"
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#include "llvm/Transforms/Utils/BuildLibCalls.h"
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#include "llvm/Transforms/Utils/BypassSlowDivision.h"
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#include "llvm/Transforms/Utils/Cloning.h"
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#include "llvm/Transforms/Utils/Local.h"
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#include "llvm/Transforms/Utils/SimplifyLibCalls.h"
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#include "llvm/Transforms/Utils/ValueMapper.h"
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using namespace llvm;
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using namespace llvm::PatternMatch;
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@ -226,7 +222,6 @@ class TypePromotionTransaction;
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unsigned CreatedInstCost);
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bool splitBranchCondition(Function &F);
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bool simplifyOffsetableRelocate(Instruction &I);
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bool splitIndirectCriticalEdges(Function &F);
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};
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}
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@ -301,10 +296,6 @@ bool CodeGenPrepare::runOnFunction(Function &F) {
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if (!DisableBranchOpts)
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EverMadeChange |= splitBranchCondition(F);
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// Split some critical edges where one of the sources is an indirect branch,
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// to help generate sane code for PHIs involving such edges.
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EverMadeChange |= splitIndirectCriticalEdges(F);
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bool MadeChange = true;
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while (MadeChange) {
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MadeChange = false;
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@ -438,152 +429,6 @@ BasicBlock *CodeGenPrepare::findDestBlockOfMergeableEmptyBlock(BasicBlock *BB) {
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return DestBB;
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}
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// Return the unique indirectbr predecessor of a block. This may return null
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// even if such a predecessor exists, if it's not useful for splitting.
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// If a predecessor is found, OtherPreds will contain all other (non-indirectbr)
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// predecessors of BB.
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static BasicBlock *
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findIBRPredecessor(BasicBlock *BB, SmallVectorImpl<BasicBlock *> &OtherPreds) {
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// If the block doesn't have any PHIs, we don't care about it, since there's
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// no point in splitting it.
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PHINode *PN = dyn_cast<PHINode>(BB->begin());
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if (!PN)
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return nullptr;
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// Verify we have exactly one IBR predecessor.
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// Conservatively bail out if one of the other predecessors is not a "regular"
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// terminator (that is, not a switch or a br).
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BasicBlock *IBB = nullptr;
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for (unsigned Pred = 0, E = PN->getNumIncomingValues(); Pred != E; ++Pred) {
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BasicBlock *PredBB = PN->getIncomingBlock(Pred);
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TerminatorInst *PredTerm = PredBB->getTerminator();
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switch (PredTerm->getOpcode()) {
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case Instruction::IndirectBr:
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if (IBB)
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return nullptr;
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IBB = PredBB;
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break;
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case Instruction::Br:
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case Instruction::Switch:
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OtherPreds.push_back(PredBB);
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continue;
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default:
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return nullptr;
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}
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}
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return IBB;
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}
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// Split critical edges where the source of the edge is an indirectbr
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// instruction. This isn't always possible, but we can handle some easy cases.
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// This is useful because MI is unable to split such critical edges,
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// which means it will not be able to sink instructions along those edges.
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// This is especially painful for indirect branches with many successors, where
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// we end up having to prepare all outgoing values in the origin block.
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//
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// Our normal algorithm for splitting critical edges requires us to update
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// the outgoing edges of the edge origin block, but for an indirectbr this
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// is hard, since it would require finding and updating the block addresses
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// the indirect branch uses. But if a block only has a single indirectbr
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// predecessor, with the others being regular branches, we can do it in a
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// different way.
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// Say we have A -> D, B -> D, I -> D where only I -> D is an indirectbr.
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// We can split D into D0 and D1, where D0 contains only the PHIs from D,
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// and D1 is the D block body. We can then duplicate D0 as D0A and D0B, and
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// create the following structure:
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// A -> D0A, B -> D0A, I -> D0B, D0A -> D1, D0B -> D1
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bool CodeGenPrepare::splitIndirectCriticalEdges(Function &F) {
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// Check whether the function has any indirectbrs, and collect which blocks
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// they may jump to. Since most functions don't have indirect branches,
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// this lowers the common case's overhead to O(Blocks) instead of O(Edges).
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SmallSetVector<BasicBlock *, 16> Targets;
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for (auto &BB : F) {
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auto *IBI = dyn_cast<IndirectBrInst>(BB.getTerminator());
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if (!IBI)
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continue;
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for (unsigned Succ = 0, E = IBI->getNumSuccessors(); Succ != E; ++Succ)
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Targets.insert(IBI->getSuccessor(Succ));
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}
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if (Targets.empty())
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return false;
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bool Changed = false;
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for (BasicBlock *Target : Targets) {
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SmallVector<BasicBlock *, 16> OtherPreds;
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BasicBlock *IBRPred = findIBRPredecessor(Target, OtherPreds);
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if (!IBRPred)
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continue;
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// Don't even think about ehpads/landingpads.
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Instruction *FirstNonPHI = Target->getFirstNonPHI();
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if (FirstNonPHI->isEHPad() || Target->isLandingPad())
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continue;
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BasicBlock *BodyBlock = Target->splitBasicBlock(FirstNonPHI, ".split");
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// It's possible Target was its own successor through an indirectbr.
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// In this case, the indirectbr now comes from BodyBlock.
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if (IBRPred == Target)
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IBRPred = BodyBlock;
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// At this point Target only has PHIs, and BodyBlock has the rest of the
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// block's body. Create a copy of Target that will be used by the "direct"
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// preds.
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ValueToValueMapTy VMap;
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BasicBlock *DirectSucc = CloneBasicBlock(Target, VMap, ".clone", &F);
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for (BasicBlock *Pred : OtherPreds)
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Pred->getTerminator()->replaceUsesOfWith(Target, DirectSucc);
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// Ok, now fix up the PHIs. We know the two blocks only have PHIs, and that
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// they are clones, so the number of PHIs are the same.
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// (a) Remove the edge coming from IBRPred from the "Direct" PHI
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// (b) Leave that as the only edge in the "Indirect" PHI.
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// (c) Merge the two in the body block.
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BasicBlock::iterator Indirect = Target->begin(),
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End = Target->getFirstNonPHI()->getIterator();
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BasicBlock::iterator Direct = DirectSucc->begin();
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BasicBlock::iterator MergeInsert = BodyBlock->getFirstInsertionPt();
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assert(&*End == Target->getTerminator() &&
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"Block was expected to only contain PHIs");
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while (Indirect != End) {
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PHINode *DirPHI = cast<PHINode>(Direct);
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PHINode *IndPHI = cast<PHINode>(Indirect);
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// Now, clean up - the direct block shouldn't get the indirect value,
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// and vice versa.
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DirPHI->removeIncomingValue(IBRPred);
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Direct++;
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// Advance the pointer here, to avoid invalidation issues when the old
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// PHI is erased.
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Indirect++;
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PHINode *NewIndPHI = PHINode::Create(IndPHI->getType(), 1, "ind", IndPHI);
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NewIndPHI->addIncoming(IndPHI->getIncomingValueForBlock(IBRPred),
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IBRPred);
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// Create a PHI in the body block, to merge the direct and indirect
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// predecessors.
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PHINode *MergePHI =
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PHINode::Create(IndPHI->getType(), 2, "merge", &*MergeInsert);
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MergePHI->addIncoming(NewIndPHI, Target);
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MergePHI->addIncoming(DirPHI, DirectSucc);
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IndPHI->replaceAllUsesWith(MergePHI);
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IndPHI->eraseFromParent();
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}
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Changed = true;
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}
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return Changed;
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}
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/// Eliminate blocks that contain only PHI nodes, debug info directives, and an
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/// unconditional branch. Passes before isel (e.g. LSR/loopsimplify) often split
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/// edges in ways that are non-optimal for isel. Start by eliminating these
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@ -47,7 +47,6 @@ L3: ; preds = %L4, %bb2
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br label %L2
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L2: ; preds = %L3, %bb2
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; THUMB-LABEL: %L1.clone
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; THUMB: muls
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%res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1]
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%phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1]
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@ -5,7 +5,7 @@ define internal i16 @foo(i16 %i) nounwind {
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entry:
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%tmp1 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1]
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%gotovar.4.0 = load i8*, i8** %tmp1, align 4 ; <i8*> [#uses=1]
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; CHECK: br .LC.0.2070(r15)
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; CHECK: br .LC.0.2070(r12)
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indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
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L5: ; preds = %bb2
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@ -17,35 +17,23 @@ entry:
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bb2: ; preds = %entry, %bb3
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%gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
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; PIC: mtctr
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; PIC-NEXT: li
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; PIC-NEXT: li
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; PIC-NEXT: li
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; PIC-NEXT: li
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; PIC-NEXT: bctr
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; PIC: li
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; PIC: b LBB
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; PIC: li
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; PIC: b LBB
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; PIC: li
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; PIC: b LBB
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; PIC: li
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; PIC: b LBB
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; STATIC: mtctr
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; STATIC-NEXT: li
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; STATIC-NEXT: li
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; STATIC-NEXT: li
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; STATIC-NEXT: li
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; STATIC-NEXT: bctr
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; STATIC: li
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; STATIC: b LBB
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; STATIC: li
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; STATIC: b LBB
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; STATIC: li
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; STATIC: b LBB
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; STATIC: li
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; STATIC: b LBB
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; PPC64: mtctr
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; PPC64-NEXT: li
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; PPC64-NEXT: li
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; PPC64-NEXT: li
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; PPC64-NEXT: li
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; PPC64-NEXT: bctr
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; PPC64: li
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; PPC64: b LBB
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; PPC64: li
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; PPC64: b LBB
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; PPC64: li
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; PPC64: b LBB
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; PPC64: li
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; PPC64: b LBB
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indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
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bb3: ; preds = %entry
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@ -1,254 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -codegenprepare -S < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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declare void @use(i32) local_unnamed_addr
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declare void @useptr([2 x i8*]*) local_unnamed_addr
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; CHECK: @simple.targets = constant [2 x i8*] [i8* blockaddress(@simple, %bb0), i8* blockaddress(@simple, %bb1)], align 16
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@simple.targets = constant [2 x i8*] [i8* blockaddress(@simple, %bb0), i8* blockaddress(@simple, %bb1)], align 16
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; CHECK: @multi.targets = constant [2 x i8*] [i8* blockaddress(@multi, %bb0), i8* blockaddress(@multi, %bb1)], align 16
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@multi.targets = constant [2 x i8*] [i8* blockaddress(@multi, %bb0), i8* blockaddress(@multi, %bb1)], align 16
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; CHECK: @loop.targets = constant [2 x i8*] [i8* blockaddress(@loop, %bb0), i8* blockaddress(@loop, %bb1)], align 16
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@loop.targets = constant [2 x i8*] [i8* blockaddress(@loop, %bb0), i8* blockaddress(@loop, %bb1)], align 16
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; CHECK: @nophi.targets = constant [2 x i8*] [i8* blockaddress(@nophi, %bb0), i8* blockaddress(@nophi, %bb1)], align 16
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@nophi.targets = constant [2 x i8*] [i8* blockaddress(@nophi, %bb0), i8* blockaddress(@nophi, %bb1)], align 16
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; Check that we break the critical edge when an jump table has only one use.
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define void @simple(i32* nocapture readonly %p) {
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; CHECK-LABEL: @simple(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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; CHECK-NEXT: [[INITVAL:%.*]] = load i32, i32* [[P]], align 4
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; CHECK-NEXT: [[INITOP:%.*]] = load i32, i32* [[INCDEC_PTR]], align 4
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; CHECK-NEXT: switch i32 [[INITOP]], label [[EXIT:%.*]] [
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; CHECK-NEXT: i32 0, label [[BB0_CLONE:%.*]]
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; CHECK-NEXT: i32 1, label [[BB1_CLONE:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb0:
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; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
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; CHECK: .split:
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; CHECK-NEXT: [[MERGE:%.*]] = phi i32* [ [[PTR:%.*]], [[BB0:%.*]] ], [ [[INCDEC_PTR]], [[BB0_CLONE]] ]
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; CHECK-NEXT: [[MERGE2:%.*]] = phi i32 [ 0, [[BB0]] ], [ [[INITVAL]], [[BB0_CLONE]] ]
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; CHECK-NEXT: tail call void @use(i32 [[MERGE2]])
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; CHECK-NEXT: br label [[INDIRECTGOTO:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: br label [[DOTSPLIT3:%.*]]
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; CHECK: .split3:
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; CHECK-NEXT: [[MERGE5:%.*]] = phi i32* [ [[PTR]], [[BB1:%.*]] ], [ [[INCDEC_PTR]], [[BB1_CLONE]] ]
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; CHECK-NEXT: [[MERGE7:%.*]] = phi i32 [ 1, [[BB1]] ], [ [[INITVAL]], [[BB1_CLONE]] ]
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; CHECK-NEXT: tail call void @use(i32 [[MERGE7]])
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; CHECK-NEXT: br label [[INDIRECTGOTO]]
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; CHECK: indirectgoto:
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; CHECK-NEXT: [[P_ADDR_SINK:%.*]] = phi i32* [ [[MERGE5]], [[DOTSPLIT3]] ], [ [[MERGE]], [[DOTSPLIT]] ]
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; CHECK-NEXT: [[PTR]] = getelementptr inbounds i32, i32* [[P_ADDR_SINK]], i64 1
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; CHECK-NEXT: [[NEWP:%.*]] = load i32, i32* [[P_ADDR_SINK]], align 4
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; CHECK-NEXT: [[IDX:%.*]] = sext i32 [[NEWP]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @simple.targets, i64 0, i64 [[IDX]]
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; CHECK-NEXT: [[NEWOP:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8
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; CHECK-NEXT: indirectbr i8* [[NEWOP]], [label [[BB0]], label %bb1]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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; CHECK: bb0.clone:
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; CHECK-NEXT: br label [[DOTSPLIT]]
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; CHECK: bb1.clone:
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; CHECK-NEXT: br label [[DOTSPLIT3]]
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;
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entry:
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%incdec.ptr = getelementptr inbounds i32, i32* %p, i64 1
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%initval = load i32, i32* %p, align 4
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%initop = load i32, i32* %incdec.ptr, align 4
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switch i32 %initop, label %exit [
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i32 0, label %bb0
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i32 1, label %bb1
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]
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bb0:
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%p.addr.0 = phi i32* [ %incdec.ptr, %entry ], [ %ptr, %indirectgoto ]
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%opcode.0 = phi i32 [ %initval, %entry ], [ 0, %indirectgoto ]
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tail call void @use(i32 %opcode.0)
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br label %indirectgoto
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bb1:
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%p.addr.1 = phi i32* [ %incdec.ptr, %entry ], [ %ptr, %indirectgoto ]
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%opcode.1 = phi i32 [ %initval, %entry ], [ 1, %indirectgoto ]
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tail call void @use(i32 %opcode.1)
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br label %indirectgoto
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indirectgoto:
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%p.addr.sink = phi i32* [ %p.addr.1, %bb1 ], [ %p.addr.0, %bb0 ]
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%ptr = getelementptr inbounds i32, i32* %p.addr.sink, i64 1
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%newp = load i32, i32* %p.addr.sink, align 4
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%idx = sext i32 %newp to i64
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%arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @simple.targets, i64 0, i64 %idx
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%newop = load i8*, i8** %arrayidx, align 8
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indirectbr i8* %newop, [label %bb0, label %bb1]
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exit:
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ret void
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}
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; Don't try to break critical edges when several indirectbr point to a single block
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define void @multi(i32* nocapture readonly %p) {
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; CHECK-LABEL: @multi(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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; CHECK-NEXT: [[INITVAL:%.*]] = load i32, i32* [[P]], align 4
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; CHECK-NEXT: [[INITOP:%.*]] = load i32, i32* [[INCDEC_PTR]], align 4
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; CHECK-NEXT: switch i32 [[INITOP]], label [[EXIT:%.*]] [
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; CHECK-NEXT: i32 0, label [[BB0:%.*]]
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; CHECK-NEXT: i32 1, label [[BB1:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb0:
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; CHECK-NEXT: [[P_ADDR_0:%.*]] = phi i32* [ [[INCDEC_PTR]], [[ENTRY:%.*]] ], [ [[NEXT0:%.*]], [[BB0]] ], [ [[NEXT1:%.*]], [[BB1]] ]
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; CHECK-NEXT: [[OPCODE_0:%.*]] = phi i32 [ [[INITVAL]], [[ENTRY]] ], [ 0, [[BB0]] ], [ 1, [[BB1]] ]
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; CHECK-NEXT: tail call void @use(i32 [[OPCODE_0]])
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; CHECK-NEXT: [[NEXT0]] = getelementptr inbounds i32, i32* [[P_ADDR_0]], i64 1
|
||||
; CHECK-NEXT: [[NEWP0:%.*]] = load i32, i32* [[P_ADDR_0]], align 4
|
||||
; CHECK-NEXT: [[IDX0:%.*]] = sext i32 [[NEWP0]] to i64
|
||||
; CHECK-NEXT: [[ARRAYIDX0:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @multi.targets, i64 0, i64 [[IDX0]]
|
||||
; CHECK-NEXT: [[NEWOP0:%.*]] = load i8*, i8** [[ARRAYIDX0]], align 8
|
||||
; CHECK-NEXT: indirectbr i8* [[NEWOP0]], [label [[BB0]], label %bb1]
|
||||
; CHECK: bb1:
|
||||
; CHECK-NEXT: [[P_ADDR_1:%.*]] = phi i32* [ [[INCDEC_PTR]], [[ENTRY]] ], [ [[NEXT0]], [[BB0]] ], [ [[NEXT1]], [[BB1]] ]
|
||||
; CHECK-NEXT: [[OPCODE_1:%.*]] = phi i32 [ [[INITVAL]], [[ENTRY]] ], [ 0, [[BB0]] ], [ 1, [[BB1]] ]
|
||||
; CHECK-NEXT: tail call void @use(i32 [[OPCODE_1]])
|
||||
; CHECK-NEXT: [[NEXT1]] = getelementptr inbounds i32, i32* [[P_ADDR_1]], i64 1
|
||||
; CHECK-NEXT: [[NEWP1:%.*]] = load i32, i32* [[P_ADDR_1]], align 4
|
||||
; CHECK-NEXT: [[IDX1:%.*]] = sext i32 [[NEWP1]] to i64
|
||||
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @multi.targets, i64 0, i64 [[IDX1]]
|
||||
; CHECK-NEXT: [[NEWOP1:%.*]] = load i8*, i8** [[ARRAYIDX1]], align 8
|
||||
; CHECK-NEXT: indirectbr i8* [[NEWOP1]], [label [[BB0]], label %bb1]
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%incdec.ptr = getelementptr inbounds i32, i32* %p, i64 1
|
||||
%initval = load i32, i32* %p, align 4
|
||||
%initop = load i32, i32* %incdec.ptr, align 4
|
||||
switch i32 %initop, label %exit [
|
||||
i32 0, label %bb0
|
||||
i32 1, label %bb1
|
||||
]
|
||||
|
||||
bb0:
|
||||
%p.addr.0 = phi i32* [ %incdec.ptr, %entry ], [ %next0, %bb0 ], [ %next1, %bb1 ]
|
||||
%opcode.0 = phi i32 [ %initval, %entry ], [ 0, %bb0 ], [ 1, %bb1 ]
|
||||
tail call void @use(i32 %opcode.0)
|
||||
%next0 = getelementptr inbounds i32, i32* %p.addr.0, i64 1
|
||||
%newp0 = load i32, i32* %p.addr.0, align 4
|
||||
%idx0 = sext i32 %newp0 to i64
|
||||
%arrayidx0 = getelementptr inbounds [2 x i8*], [2 x i8*]* @multi.targets, i64 0, i64 %idx0
|
||||
%newop0 = load i8*, i8** %arrayidx0, align 8
|
||||
indirectbr i8* %newop0, [label %bb0, label %bb1]
|
||||
|
||||
bb1:
|
||||
%p.addr.1 = phi i32* [ %incdec.ptr, %entry ], [ %next0, %bb0 ], [ %next1, %bb1 ]
|
||||
%opcode.1 = phi i32 [ %initval, %entry ], [ 0, %bb0 ], [ 1, %bb1 ]
|
||||
tail call void @use(i32 %opcode.1)
|
||||
%next1 = getelementptr inbounds i32, i32* %p.addr.1, i64 1
|
||||
%newp1 = load i32, i32* %p.addr.1, align 4
|
||||
%idx1 = sext i32 %newp1 to i64
|
||||
%arrayidx1 = getelementptr inbounds [2 x i8*], [2 x i8*]* @multi.targets, i64 0, i64 %idx1
|
||||
%newop1 = load i8*, i8** %arrayidx1, align 8
|
||||
indirectbr i8* %newop1, [label %bb0, label %bb1]
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Make sure we do the right thing for cases where the indirectbr branches to
|
||||
; the block it terminates.
|
||||
define void @loop(i64* nocapture readonly %p) {
|
||||
; CHECK-LABEL: @loop(
|
||||
; CHECK-NEXT: bb0.clone:
|
||||
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
|
||||
; CHECK: bb0:
|
||||
; CHECK-NEXT: br label [[DOTSPLIT]]
|
||||
; CHECK: .split:
|
||||
; CHECK-NEXT: [[MERGE:%.*]] = phi i64 [ [[I_NEXT:%.*]], [[BB0:%.*]] ], [ 0, [[BB0_CLONE:%.*]] ]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i64, i64* [[P:%.*]], i64 [[MERGE]]
|
||||
; CHECK-NEXT: store i64 [[MERGE]], i64* [[TMP0]], align 4
|
||||
; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[MERGE]], 1
|
||||
; CHECK-NEXT: [[IDX:%.*]] = srem i64 [[MERGE]], 2
|
||||
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @loop.targets, i64 0, i64 [[IDX]]
|
||||
; CHECK-NEXT: [[TARGET:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8
|
||||
; CHECK-NEXT: indirectbr i8* [[TARGET]], [label [[BB0]], label %bb1]
|
||||
; CHECK: bb1:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %bb0
|
||||
|
||||
bb0:
|
||||
%i = phi i64 [ %i.next, %bb0 ], [ 0, %entry ]
|
||||
%tmp0 = getelementptr inbounds i64, i64* %p, i64 %i
|
||||
store i64 %i, i64* %tmp0, align 4
|
||||
%i.next = add nuw nsw i64 %i, 1
|
||||
%idx = srem i64 %i, 2
|
||||
%arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @loop.targets, i64 0, i64 %idx
|
||||
%target = load i8*, i8** %arrayidx, align 8
|
||||
indirectbr i8* %target, [label %bb0, label %bb1]
|
||||
|
||||
bb1:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Don't do anything for cases that contain no phis.
|
||||
define void @nophi(i32* %p) {
|
||||
; CHECK-LABEL: @nophi(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
|
||||
; CHECK-NEXT: [[INITOP:%.*]] = load i32, i32* [[INCDEC_PTR]], align 4
|
||||
; CHECK-NEXT: switch i32 [[INITOP]], label [[EXIT:%.*]] [
|
||||
; CHECK-NEXT: i32 0, label [[BB0:%.*]]
|
||||
; CHECK-NEXT: i32 1, label [[BB1:%.*]]
|
||||
; CHECK-NEXT: ]
|
||||
; CHECK: bb0:
|
||||
; CHECK-NEXT: tail call void @use(i32 0)
|
||||
; CHECK-NEXT: br label [[INDIRECTGOTO:%.*]]
|
||||
; CHECK: bb1:
|
||||
; CHECK-NEXT: tail call void @use(i32 1)
|
||||
; CHECK-NEXT: br label [[INDIRECTGOTO]]
|
||||
; CHECK: indirectgoto:
|
||||
; CHECK-NEXT: [[SUNKADDR:%.*]] = ptrtoint i32* [[P]] to i64
|
||||
; CHECK-NEXT: [[SUNKADDR1:%.*]] = add i64 [[SUNKADDR]], 4
|
||||
; CHECK-NEXT: [[SUNKADDR2:%.*]] = inttoptr i64 [[SUNKADDR1]] to i32*
|
||||
; CHECK-NEXT: [[NEWP:%.*]] = load i32, i32* [[SUNKADDR2]], align 4
|
||||
; CHECK-NEXT: [[IDX:%.*]] = sext i32 [[NEWP]] to i64
|
||||
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @nophi.targets, i64 0, i64 [[IDX]]
|
||||
; CHECK-NEXT: [[NEWOP:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8
|
||||
; CHECK-NEXT: indirectbr i8* [[NEWOP]], [label [[BB0]], label %bb1]
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%incdec.ptr = getelementptr inbounds i32, i32* %p, i64 1
|
||||
%initop = load i32, i32* %incdec.ptr, align 4
|
||||
switch i32 %initop, label %exit [
|
||||
i32 0, label %bb0
|
||||
i32 1, label %bb1
|
||||
]
|
||||
|
||||
bb0:
|
||||
tail call void @use(i32 0)
|
||||
br label %indirectgoto
|
||||
|
||||
bb1:
|
||||
tail call void @use(i32 1)
|
||||
br label %indirectgoto
|
||||
|
||||
indirectgoto:
|
||||
%newp = load i32, i32* %incdec.ptr, align 4
|
||||
%idx = sext i32 %newp to i64
|
||||
%arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @nophi.targets, i64 0, i64 %idx
|
||||
%newop = load i8*, i8** %arrayidx, align 8
|
||||
indirectbr i8* %newop, [label %bb0, label %bb1]
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
Loading…
Reference in New Issue