From 3c9ed76ba5294b6c7c2070008818e42e94aa99c8 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Fri, 13 Aug 2010 22:43:33 +0000 Subject: [PATCH] Temporarily disable tail calls on ARM to work around some linker problems. llvm-svn: 111050 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 9 +++++++++ llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll | 1 + llvm/test/CodeGen/ARM/call-tc.ll | 1 + llvm/test/CodeGen/Thumb2/thumb2-call-tc.ll | 1 + llvm/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll | 1 + 5 files changed, 13 insertions(+) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 073528abe8dc..5a03a07dccac 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -51,6 +51,12 @@ using namespace llvm; STATISTIC(NumTailCalls, "Number of tail calls"); +// This option should go away when tail calls fully work. +static cl::opt +EnableARMTailCalls("arm-tail-calls", cl::Hidden, + cl::desc("Generate tail calls (TEMPORARY OPTION)."), + cl::init(false)); + // This option should go away when Machine LICM is smart enough to hoist a // reg-to-reg VDUP. static cl::opt @@ -1117,6 +1123,9 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, MachineFunction &MF = DAG.getMachineFunction(); bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); bool IsSibCall = false; + // Temporarily disable tail calls so things don't break. + if (!EnableARMTailCalls) + isTailCall = false; if (isTailCall) { // Check if it's really possible to do a tail call. isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, diff --git a/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll b/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll index 7650d883d7b1..ac8e80904eda 100755 --- a/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll +++ b/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=arm -mtriple=armv4t-unknown-linux-gnueabi | FileCheck %s ; PR 7433 +; XFAIL: * %0 = type { i8*, i8* } %1 = type { i8*, i8*, i8* } diff --git a/llvm/test/CodeGen/ARM/call-tc.ll b/llvm/test/CodeGen/ARM/call-tc.ll index f1269d5bd2be..db5afe3f56cb 100644 --- a/llvm/test/CodeGen/ARM/call-tc.ll +++ b/llvm/test/CodeGen/ARM/call-tc.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ ; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF +; XFAIL: * @t = weak global i32 ()* null ; [#uses=1] diff --git a/llvm/test/CodeGen/Thumb2/thumb2-call-tc.ll b/llvm/test/CodeGen/Thumb2/thumb2-call-tc.ll index 24502b0338c2..2e4da1b289b5 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-call-tc.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-call-tc.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s -check-prefix=DARWIN ; RUN: llc < %s -mtriple=thumbv7-linux -mattr=+thumb2 | FileCheck %s -check-prefix=LINUX +; XFAIL: * @t = weak global i32 ()* null ; [#uses=1] diff --git a/llvm/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll b/llvm/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll index c02441547718..5315535db045 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +; XFAIL: * define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK: t1: