forked from OSchip/llvm-project
[NFC][ARM] Add tail predication test
This commit is contained in:
Sam Parker
parent
2a3498e24f
commit
3c9b6dfa54
|
|
@ -0,0 +1,166 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
|
||||
--- |
|
||||
|
||||
; Function Attrs: nofree norecurse nounwind
|
||||
define dso_local arm_aapcs_vfpcc void @test(i32* noalias nocapture %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%cmp9 = icmp eq i32 %N, 0
|
||||
%0 = add i32 %N, 3
|
||||
%1 = lshr i32 %0, 2
|
||||
%2 = shl nuw i32 %1, 2
|
||||
%3 = add i32 %2, -4
|
||||
%4 = lshr i32 %3, 2
|
||||
%5 = add nuw nsw i32 %4, 1
|
||||
br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
|
||||
|
||||
vector.ph: ; preds = %entry
|
||||
%div = lshr i32 %N, 1
|
||||
%trip.count.minus.1 = add i32 %N, -1
|
||||
%broadcast.splatinsert = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0
|
||||
%broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
call void @llvm.set.loop.iterations.i32(i32 %5)
|
||||
br label %vector.body
|
||||
|
||||
vector.body: ; preds = %vector.body, %vector.ph
|
||||
%lsr.iv3 = phi i32* [ %scevgep4, %vector.body ], [ %b, %vector.ph ]
|
||||
%lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
|
||||
%vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ]
|
||||
%elts.rem = phi i32 [ %N, %vector.ph ], [ %elts.rem.next, %vector.body ]
|
||||
%6 = phi i32 [ %5, %vector.ph ], [ %12, %vector.body ]
|
||||
%lsr.iv35 = bitcast i32* %lsr.iv3 to <4 x i32>*
|
||||
%lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>*
|
||||
%7 = insertelement <4 x i32> undef, i32 %div, i32 0
|
||||
%8 = shufflevector <4 x i32> %7, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
%9 = icmp ult <4 x i32> %vec.ind, %8
|
||||
%10 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %elts.rem)
|
||||
%11 = and <4 x i1> %9, %10
|
||||
%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv35, i32 4, <4 x i1> %11, <4 x i32> undef)
|
||||
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %wide.masked.load, <4 x i32>* %lsr.iv12, i32 4, <4 x i1> %11)
|
||||
%vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>
|
||||
%elts.rem.next = sub i32 %elts.rem, 4
|
||||
%scevgep = getelementptr i32, i32* %lsr.iv1, i32 4
|
||||
%scevgep4 = getelementptr i32, i32* %lsr.iv3, i32 4
|
||||
%12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
|
||||
%13 = icmp ne i32 %12, 0
|
||||
br i1 %13, label %vector.body, label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %vector.body, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
|
||||
...
|
||||
---
|
||||
name: test
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
registers: []
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '' }
|
||||
- { reg: '$r1', virtual-reg: '' }
|
||||
- { reg: '$r2', virtual-reg: '' }
|
||||
frameInfo:
|
||||
stackSize: 8
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 4
|
||||
fixedStack: []
|
||||
stack:
|
||||
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
callSites: []
|
||||
constants:
|
||||
- id: 0
|
||||
value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'
|
||||
alignment: 16
|
||||
isTargetSpecific: false
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: test
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $lr, $r0, $r1, $r2
|
||||
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
|
||||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
|
||||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
|
||||
; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||||
; CHECK: t2IT 0, 8, implicit-def $itstate
|
||||
; CHECK: frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
|
||||
; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2
|
||||
; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool)
|
||||
; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
|
||||
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1
|
||||
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
|
||||
; CHECK: bb.1.vector.body:
|
||||
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1
|
||||
; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, killed $noreg
|
||||
; CHECK: MVE_VPST 4, implicit $vpr
|
||||
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv35, align 4)
|
||||
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv12, align 4)
|
||||
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0
|
||||
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
|
||||
; CHECK: bb.2.for.cond.cleanup:
|
||||
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||||
; CHECK: bb.3 (align 16):
|
||||
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x80000000)
|
||||
liveins: $r0, $r1, $r2, $lr
|
||||
|
||||
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
|
||||
frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
$r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
|
||||
frame-setup CFI_INSTRUCTION def_cfa_register $r7
|
||||
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||||
t2IT 0, 8, implicit-def $itstate
|
||||
frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
|
||||
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
|
||||
renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2
|
||||
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
|
||||
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
|
||||
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
|
||||
renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
|
||||
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool)
|
||||
renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
|
||||
renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1
|
||||
t2DoLoopStart renamable $lr
|
||||
|
||||
bb.1.vector.body:
|
||||
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
|
||||
|
||||
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
|
||||
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
|
||||
MVE_VPST 2, implicit $vpr
|
||||
renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr
|
||||
renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv35, align 4)
|
||||
renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv12, align 4)
|
||||
renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
|
||||
tB %bb.2, 14 /* CC::al */, $noreg
|
||||
|
||||
bb.2.for.cond.cleanup:
|
||||
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||||
|
||||
bb.3 (align 16):
|
||||
CONSTPOOL_ENTRY 0, %const.0, 16
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue