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[X86] Reduce scope of variables where possible. NFCI. 

Fixes cppcheck warnings.

llvm-svn: 360131
This commit is contained in:
Simon Pilgrim 2019-05-07 10:50:11 +00:00
parent d6d3808fa4
commit 3c975a0ab5
3 changed files with 4 additions and 10 deletions
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2
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -3342,7 +3342,6 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
int CmpValue, int CmpValue,
const MachineRegisterInfo *MRI) const { const MachineRegisterInfo *MRI) const {
// Check whether we can replace SUB with CMP. // Check whether we can replace SUB with CMP.
unsigned NewOpcode = 0;
switch (CmpInstr.getOpcode()) { switch (CmpInstr.getOpcode()) {
default: break; default: break;
case X86::SUB64ri32: case X86::SUB64ri32:
@ -3363,6 +3362,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg())) if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
return false; return false;
// There is no use of the destination register, we can replace SUB with CMP. // There is no use of the destination register, we can replace SUB with CMP.
unsigned NewOpcode = 0;
switch (CmpInstr.getOpcode()) { switch (CmpInstr.getOpcode()) {
default: llvm_unreachable("Unreachable!"); default: llvm_unreachable("Unreachable!");
case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;

7
llvm/lib/Target/X86/X86PadShortFunction.cpp
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@ -112,14 +112,11 @@ bool PadShortFunc::runOnMachineFunction(MachineFunction &MF) {
bool MadeChange = false; bool MadeChange = false;
MachineBasicBlock *MBB;
unsigned int Cycles = 0;
// Pad the identified basic blocks with NOOPs // Pad the identified basic blocks with NOOPs
for (DenseMap<MachineBasicBlock*, unsigned int>::iterator I = ReturnBBs.begin(); for (DenseMap<MachineBasicBlock*, unsigned int>::iterator I = ReturnBBs.begin();
I != ReturnBBs.end(); ++I) { I != ReturnBBs.end(); ++I) {
MBB = I->first; MachineBasicBlock *MBB = I->first;
Cycles = I->second; unsigned Cycles = I->second;
if (Cycles < Threshold) { if (Cycles < Threshold) {
// BB ends in a return. Skip over any DBG_VALUE instructions // BB ends in a return. Skip over any DBG_VALUE instructions

5
llvm/lib/Target/X86/X86RegisterBankInfo.cpp
View File

@ -159,7 +159,7 @@ const RegisterBankInfo::InstructionMapping &
X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent(); const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo(); const MachineRegisterInfo &MRI = MF.getRegInfo();
auto Opc = MI.getOpcode(); unsigned Opc = MI.getOpcode();
// Try the default logic for non-generic instructions that are either copies // Try the default logic for non-generic instructions that are either copies
// or already have some operands assigned to banks. // or already have some operands assigned to banks.
@ -182,9 +182,6 @@ X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_SHL: case TargetOpcode::G_SHL:
case TargetOpcode::G_LSHR: case TargetOpcode::G_LSHR:
case TargetOpcode::G_ASHR: { case TargetOpcode::G_ASHR: {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
unsigned NumOperands = MI.getNumOperands(); unsigned NumOperands = MI.getNumOperands();
LLT Ty = MRI.getType(MI.getOperand(0).getReg()); LLT Ty = MRI.getType(MI.getOperand(0).getReg());