forked from OSchip/llvm-project
[mips] MUL macro variations
[mips] MUL macro variations Adds support for MUL macro variations. Patch by: Srdjan Obucina Reviewers: zoran.jovanovic, vkalintiris, dsanders, sdardis, obucina, seanbruno Differential Revision: https://reviews.llvm.org/D16807 llvm-svn: 294471
This commit is contained in:
Simon Dardis
parent
6dd2eae76a
commit
3c82a64636
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@ -276,6 +276,18 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI, bool IsLoad);
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@ -2332,6 +2344,17 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::ABSMacro:
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return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::MULImmMacro:
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case Mips::DMULImmMacro:
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return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::MULOMacro:
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case Mips::DMULOMacro:
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return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::MULOUMacro:
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case Mips::DMULOUMacro:
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return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::DMULMacro:
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return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::LDMacro:
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case Mips::SDMacro:
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return expandLoadStoreDMacro(Inst, IDLoc, Out, STI,
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@ -4060,6 +4083,119 @@ bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return false;
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}
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bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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unsigned ATReg = Mips::NoRegister;
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unsigned DstReg = Inst.getOperand(0).getReg();
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unsigned SrcReg = Inst.getOperand(1).getReg();
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int32_t ImmValue = Inst.getOperand(2).getImm();
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ATReg = getATReg(IDLoc);
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if (!ATReg)
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return true;
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loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, STI);
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TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT,
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SrcReg, ATReg, IDLoc, STI);
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TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
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return false;
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}
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bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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unsigned ATReg = Mips::NoRegister;
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unsigned DstReg = Inst.getOperand(0).getReg();
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unsigned SrcReg = Inst.getOperand(1).getReg();
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unsigned TmpReg = Inst.getOperand(2).getReg();
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ATReg = getATReg(Inst.getLoc());
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if (!ATReg)
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return true;
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TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT,
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SrcReg, TmpReg, IDLoc, STI);
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TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
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TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32,
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DstReg, DstReg, 0x1F, IDLoc, STI);
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TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
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if (useTraps()) {
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TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI);
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} else {
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MCContext & Context = TOut.getStreamer().getContext();
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MCSymbol * BrTarget = Context.createTempSymbol();
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MCOperand LabelOp =
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MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
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TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI);
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if (AssemblerOptions.back()->isReorder())
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TOut.emitNop(IDLoc, STI);
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TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
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TOut.getStreamer().EmitLabel(BrTarget);
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}
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TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
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return false;
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}
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bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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unsigned ATReg = Mips::NoRegister;
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unsigned DstReg = Inst.getOperand(0).getReg();
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unsigned SrcReg = Inst.getOperand(1).getReg();
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unsigned TmpReg = Inst.getOperand(2).getReg();
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ATReg = getATReg(IDLoc);
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if (!ATReg)
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return true;
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TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu,
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SrcReg, TmpReg, IDLoc, STI);
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TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
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TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
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if (useTraps()) {
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TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI);
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} else {
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MCContext & Context = TOut.getStreamer().getContext();
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MCSymbol * BrTarget = Context.createTempSymbol();
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MCOperand LabelOp =
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MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
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TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);
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if (AssemblerOptions.back()->isReorder())
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TOut.emitNop(IDLoc, STI);
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TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
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TOut.getStreamer().EmitLabel(BrTarget);
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}
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return false;
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}
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bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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unsigned DstReg = Inst.getOperand(0).getReg();
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unsigned SrcReg = Inst.getOperand(1).getReg();
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unsigned TmpReg = Inst.getOperand(2).getReg();
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TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);
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TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
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return false;
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}
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static unsigned nextReg(unsigned Reg) {
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switch (Reg) {
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case Mips::ZERO: return Mips::AT;
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@ -738,14 +738,13 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
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void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
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auto *Symbol = cast<MCSymbolELF>(S);
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if (!isMicroMipsEnabled())
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return;
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getStreamer().getAssembler().registerSymbol(*Symbol);
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uint8_t Type = Symbol->getType();
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if (Type != ELF::STT_FUNC)
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return;
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Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
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if (isMicroMipsEnabled())
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Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
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}
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void MipsTargetELFStreamer::finish() {
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@ -816,3 +816,22 @@ def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr),
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"dla\t$rt, $addr">;
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def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64),
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"dla\t$rt, $imm64">;
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def DMULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
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simm32_relaxed:$imm),
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"dmul\t$rs, $rt, $imm">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DMULOMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
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GPR64Opnd:$rd),
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"dmulo\t$rs, $rt, $rd">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DMULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
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GPR64Opnd:$rd),
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"dmulou\t$rs, $rt, $rd">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DMULMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
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GPR64Opnd:$rd),
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"dmul\t$rs, $rt, $rd"> {
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let InsnPredicates = [HasMips3, NotMips64r6, NotCnMips];
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}
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@ -2303,6 +2303,20 @@ def SEQIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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def : MipsInstAlias<"seq $rd, $imm",
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(SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>,
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NOT_ASE_CNMIPS;
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def MULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,
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simm32_relaxed:$imm),
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"mul\t$rd, $rs, $imm">,
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ISA_MIPS1_NOT_32R6_64R6;
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def MULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,
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GPR32Opnd:$rt),
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"mulo\t$rd, $rs, $rt">,
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ISA_MIPS1_NOT_32R6_64R6;
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def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,
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GPR32Opnd:$rt),
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"mulou\t$rd, $rs, $rt">,
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ISA_MIPS1_NOT_32R6_64R6;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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@ -2467,6 +2481,14 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
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def : MipsInstAlias<"sync",
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(SYNC 0), 1>, ISA_MIPS2;
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def : MipsInstAlias<"mulo $rs, $rt",
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(MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"mulou $rs, $rt",
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(MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions
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//===----------------------------------------------------------------------===//
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