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[Instcombine][NFC]Simplify logical reductions tests, NFC.

This commit is contained in:
Alexey Bataev 2021-03-02 08:23:50 -08:00
parent 6e967834b9
commit 3c3c4ee24f
1 changed files with 10 additions and 18 deletions
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28
llvm/test/Transforms/InstCombine/vector-logical-reductions.ll
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@ -1,30 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
define float @reduction_logical_or(<4 x float> %x) {
define i1 @reduction_logical_or(<4 x i1> %x) {
; CHECK-LABEL: @reduction_logical_or(
; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt <4 x float> [[X:%.*]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP1]])
; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP2]], float -1.000000e+00, float 1.000000e+00
; CHECK-NEXT: ret float [[R]]
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%1 = fcmp ogt <4 x float> %x, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
%2 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %1)
%r = select i1 %2, float -1.000000e+00, float 1.000000e+00
ret float %r
%r = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %x)
ret i1 %r
}
define float @reduction_logical_and(<4 x float> %x) {
define i1 @reduction_logical_and(<4 x i1> %x) {
; CHECK-LABEL: @reduction_logical_and(
; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt <4 x float> [[X:%.*]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP1]])
; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP2]], float -1.000000e+00, float 1.000000e+00
; CHECK-NEXT: ret float [[R]]
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[X:%.*]])
; CHECK-NEXT: ret i1 [[R]]
;
%1 = fcmp ogt <4 x float> %x, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
%2 = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %1)
%r = select i1 %2, float -1.000000e+00, float 1.000000e+00
ret float %r
%r = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %x)
ret i1 %r
}
declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)