forked from OSchip/llvm-project
bpf: refactor inst patterns with more mnemonics
Currently, eBPF backend is using some constant directly in instruction patterns, This patch replace them with mnemonics and removed some unnecessary temparary variables. Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 313958
This commit is contained in:
Yonghong Song
parent
7ff8304db7
commit
3bf1a8d04e
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@ -7,6 +7,86 @@
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//
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//===----------------------------------------------------------------------===//
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class BPFOpClass<bits<3> val> {
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bits<3> Value = val;
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}
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def BPF_LD : BPFOpClass<0x0>;
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def BPF_LDX : BPFOpClass<0x1>;
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def BPF_ST : BPFOpClass<0x2>;
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def BPF_STX : BPFOpClass<0x3>;
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def BPF_ALU : BPFOpClass<0x4>;
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def BPF_JMP : BPFOpClass<0x5>;
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def BPF_ALU64 : BPFOpClass<0x7>;
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class BPFSrcType<bits<1> val> {
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bits<1> Value = val;
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}
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def BPF_K : BPFSrcType<0x0>;
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def BPF_X : BPFSrcType<0x1>;
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class BPFArithOp<bits<4> val> {
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bits<4> Value = val;
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}
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def BPF_ADD : BPFArithOp<0x0>;
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def BPF_SUB : BPFArithOp<0x1>;
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def BPF_MUL : BPFArithOp<0x2>;
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def BPF_DIV : BPFArithOp<0x3>;
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def BPF_OR : BPFArithOp<0x4>;
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def BPF_AND : BPFArithOp<0x5>;
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def BPF_LSH : BPFArithOp<0x6>;
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def BPF_RSH : BPFArithOp<0x7>;
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def BPF_XOR : BPFArithOp<0xa>;
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def BPF_MOV : BPFArithOp<0xb>;
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def BPF_ARSH : BPFArithOp<0xc>;
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def BPF_END : BPFArithOp<0xd>;
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class BPFEndDir<bits<1> val> {
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bits<1> Value = val;
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}
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def BPF_TO_LE : BPFSrcType<0x0>;
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def BPF_TO_BE : BPFSrcType<0x1>;
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class BPFJumpOp<bits<4> val> {
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bits<4> Value = val;
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}
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def BPF_JA : BPFJumpOp<0x0>;
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def BPF_JEQ : BPFJumpOp<0x1>;
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def BPF_JGT : BPFJumpOp<0x2>;
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def BPF_JGE : BPFJumpOp<0x3>;
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def BPF_JNE : BPFJumpOp<0x5>;
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def BPF_JSGT : BPFJumpOp<0x6>;
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def BPF_JSGE : BPFJumpOp<0x7>;
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def BPF_CALL : BPFJumpOp<0x8>;
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def BPF_EXIT : BPFJumpOp<0x9>;
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def BPF_JLT : BPFJumpOp<0xa>;
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def BPF_JLE : BPFJumpOp<0xb>;
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def BPF_JSLT : BPFJumpOp<0xc>;
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def BPF_JSLE : BPFJumpOp<0xd>;
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class BPFWidthModifer<bits<2> val> {
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bits<2> Value = val;
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}
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def BPF_W : BPFWidthModifer<0x0>;
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def BPF_H : BPFWidthModifer<0x1>;
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def BPF_B : BPFWidthModifer<0x2>;
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def BPF_DW : BPFWidthModifer<0x3>;
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class BPFModeModifer<bits<3> val> {
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bits<3> Value = val;
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}
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def BPF_IMM : BPFModeModifer<0x0>;
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def BPF_ABS : BPFModeModifer<0x1>;
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def BPF_IND : BPFModeModifer<0x2>;
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def BPF_MEM : BPFModeModifer<0x3>;
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def BPF_XADD : BPFModeModifer<0x6>;
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class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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field bits<64> Inst;
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@ -16,8 +96,8 @@ class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
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let Namespace = "BPF";
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let DecoderNamespace = "BPF";
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bits<3> BPFClass;
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let Inst{58-56} = BPFClass;
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BPFOpClass BPFClass;
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let Inst{58-56} = BPFClass.Value;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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@ -89,162 +89,138 @@ def BPF_CC_LEU : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETULE);}]>;
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// jump instructions
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class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
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class JMP_RR<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
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: InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
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"if $dst "#OpcodeStr#" $src goto $BrDst",
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[(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
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bits<4> op;
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bits<1> BPFSrc;
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bits<4> dst;
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bits<4> src;
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bits<16> BrDst;
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let Inst{63-60} = op;
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let Inst{59} = BPFSrc;
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let Inst{63-60} = Opc.Value;
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let Inst{59} = BPF_X.Value;
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let Inst{55-52} = src;
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let Inst{51-48} = dst;
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let Inst{47-32} = BrDst;
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let op = Opc;
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let BPFSrc = 1;
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let BPFClass = 5; // BPF_JMP
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let BPFClass = BPF_JMP;
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}
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class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
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class JMP_RI<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
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: InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
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"if $dst "#OpcodeStr#" $imm goto $BrDst",
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[(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
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bits<4> op;
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bits<1> BPFSrc;
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bits<4> dst;
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bits<16> BrDst;
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bits<32> imm;
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let Inst{63-60} = op;
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let Inst{59} = BPFSrc;
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let Inst{63-60} = Opc.Value;
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let Inst{59} = BPF_K.Value;
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let Inst{51-48} = dst;
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let Inst{47-32} = BrDst;
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let Inst{31-0} = imm;
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let op = Opc;
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let BPFSrc = 0;
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let BPFClass = 5; // BPF_JMP
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let BPFClass = BPF_JMP;
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}
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multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> {
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multiclass J<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> {
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def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
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def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
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}
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let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
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// cmp+goto instructions
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defm JEQ : J<0x1, "==", BPF_CC_EQ>;
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defm JUGT : J<0x2, ">", BPF_CC_GTU>;
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defm JUGE : J<0x3, ">=", BPF_CC_GEU>;
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defm JNE : J<0x5, "!=", BPF_CC_NE>;
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defm JSGT : J<0x6, "s>", BPF_CC_GT>;
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defm JSGE : J<0x7, "s>=", BPF_CC_GE>;
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defm JULT : J<0xa, "<", BPF_CC_LTU>;
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defm JULE : J<0xb, "<=", BPF_CC_LEU>;
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defm JSLT : J<0xc, "s<", BPF_CC_LT>;
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defm JSLE : J<0xd, "s<=", BPF_CC_LE>;
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defm JEQ : J<BPF_JEQ, "==", BPF_CC_EQ>;
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defm JUGT : J<BPF_JGT, ">", BPF_CC_GTU>;
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defm JUGE : J<BPF_JGE, ">=", BPF_CC_GEU>;
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defm JNE : J<BPF_JNE, "!=", BPF_CC_NE>;
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defm JSGT : J<BPF_JSGT, "s>", BPF_CC_GT>;
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defm JSGE : J<BPF_JSGE, "s>=", BPF_CC_GE>;
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defm JULT : J<BPF_JLT, "<", BPF_CC_LTU>;
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defm JULE : J<BPF_JLE, "<=", BPF_CC_LEU>;
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defm JSLT : J<BPF_JSLT, "s<", BPF_CC_LT>;
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defm JSLE : J<BPF_JSLE, "s<=", BPF_CC_LE>;
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}
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// ALU instructions
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class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
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class ALU_RI<BPFArithOp Opc, string OpcodeStr, SDNode OpNode>
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: InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
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"$dst "#OpcodeStr#" $imm",
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[(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
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bits<4> op;
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bits<1> BPFSrc;
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bits<4> dst;
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bits<32> imm;
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let Inst{63-60} = op;
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let Inst{59} = BPFSrc;
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let Inst{63-60} = Opc.Value;
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let Inst{59} = BPF_K.Value;
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let Inst{51-48} = dst;
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let Inst{31-0} = imm;
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let op = Opc;
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let BPFSrc = 0;
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let BPFClass = 7; // BPF_ALU64
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let BPFClass = BPF_ALU64;
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}
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class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
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class ALU_RR<BPFArithOp Opc, string OpcodeStr, SDNode OpNode>
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: InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
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"$dst "#OpcodeStr#" $src",
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[(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
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bits<4> op;
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bits<1> BPFSrc;
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bits<4> dst;
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bits<4> src;
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let Inst{63-60} = op;
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let Inst{59} = BPFSrc;
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let Inst{63-60} = Opc.Value;
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let Inst{59} = BPF_X.Value;
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let Inst{55-52} = src;
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let Inst{51-48} = dst;
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let op = Opc;
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let BPFSrc = 1;
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let BPFClass = 7; // BPF_ALU64
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let BPFClass = BPF_ALU64;
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}
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multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
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multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
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def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
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def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
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}
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let Constraints = "$dst = $src2" in {
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let isAsCheapAsAMove = 1 in {
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defm ADD : ALU<0x0, "+=", add>;
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defm SUB : ALU<0x1, "-=", sub>;
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defm OR : ALU<0x4, "|=", or>;
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defm AND : ALU<0x5, "&=", and>;
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defm SLL : ALU<0x6, "<<=", shl>;
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defm SRL : ALU<0x7, ">>=", srl>;
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defm XOR : ALU<0xa, "^=", xor>;
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defm SRA : ALU<0xc, "s>>=", sra>;
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defm ADD : ALU<BPF_ADD, "+=", add>;
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defm SUB : ALU<BPF_SUB, "-=", sub>;
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defm OR : ALU<BPF_OR, "|=", or>;
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defm AND : ALU<BPF_AND, "&=", and>;
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defm SLL : ALU<BPF_LSH, "<<=", shl>;
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defm SRL : ALU<BPF_RSH, ">>=", srl>;
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defm XOR : ALU<BPF_XOR, "^=", xor>;
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defm SRA : ALU<BPF_ARSH, "s>>=", sra>;
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}
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defm MUL : ALU<0x2, "*=", mul>;
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defm DIV : ALU<0x3, "/=", udiv>;
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defm MUL : ALU<BPF_MUL, "*=", mul>;
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defm DIV : ALU<BPF_DIV, "/=", udiv>;
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}
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class MOV_RR<string OpcodeStr>
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: InstBPF<(outs GPR:$dst), (ins GPR:$src),
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"$dst "#OpcodeStr#" $src",
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[]> {
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bits<4> op;
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bits<1> BPFSrc;
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bits<4> dst;
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bits<4> src;
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let Inst{63-60} = op;
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let Inst{59} = BPFSrc;
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let Inst{63-60} = BPF_MOV.Value;
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let Inst{59} = BPF_X.Value;
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let Inst{55-52} = src;
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let Inst{51-48} = dst;
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let op = 0xb; // BPF_MOV
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let BPFSrc = 1; // BPF_X
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let BPFClass = 7; // BPF_ALU64
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let BPFClass = BPF_ALU64;
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}
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class MOV_RI<string OpcodeStr>
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: InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
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"$dst "#OpcodeStr#" $imm",
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[(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
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bits<4> op;
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bits<1> BPFSrc;
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bits<4> dst;
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bits<32> imm;
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let Inst{63-60} = op;
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let Inst{59} = BPFSrc;
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let Inst{63-60} = BPF_MOV.Value;
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let Inst{59} = BPF_K.Value;
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let Inst{51-48} = dst;
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let Inst{31-0} = imm;
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let op = 0xb; // BPF_MOV
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let BPFSrc = 0; // BPF_K
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let BPFClass = 7; // BPF_ALU64
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let BPFClass = BPF_ALU64;
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}
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class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
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@ -252,21 +228,17 @@ class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
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"$dst "#OpcodeStr#" ${imm} ll",
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[(set GPR:$dst, (i64 imm:$imm))]> {
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bits<3> mode;
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bits<2> size;
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bits<4> dst;
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bits<64> imm;
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let Inst{63-61} = mode;
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let Inst{60-59} = size;
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let Inst{63-61} = BPF_IMM.Value;
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let Inst{60-59} = BPF_DW.Value;
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let Inst{51-48} = dst;
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let Inst{55-52} = Pseudo;
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let Inst{47-32} = 0;
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let Inst{31-0} = imm{31-0};
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let mode = 0; // BPF_IMM
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let size = 3; // BPF_DW
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let BPFClass = 0; // BPF_LD
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let BPFClass = BPF_LD;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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@ -287,7 +259,7 @@ def FI_ri
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let Inst{55-52} = 2;
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let Inst{47-32} = 0;
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let Inst{31-0} = 0;
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let BPFClass = 0;
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let BPFClass = BPF_LD;
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}
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@ -296,115 +268,95 @@ def LD_pseudo
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"ld_pseudo\t$dst, $pseudo, $imm",
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[(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
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bits<3> mode;
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bits<2> size;
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bits<4> dst;
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bits<64> imm;
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bits<4> pseudo;
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let Inst{63-61} = mode;
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let Inst{60-59} = size;
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let Inst{63-61} = BPF_IMM.Value;
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let Inst{60-59} = BPF_DW.Value;
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let Inst{51-48} = dst;
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let Inst{55-52} = pseudo;
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let Inst{47-32} = 0;
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let Inst{31-0} = imm{31-0};
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let mode = 0; // BPF_IMM
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let size = 3; // BPF_DW
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let BPFClass = 0; // BPF_LD
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let BPFClass = BPF_LD;
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}
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// STORE instructions
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class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
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class STORE<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
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: InstBPF<(outs), (ins GPR:$src, MEMri:$addr),
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"*("#OpcodeStr#" *)($addr) = $src", Pattern> {
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bits<3> mode;
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bits<2> size;
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bits<4> src;
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bits<20> addr;
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let Inst{63-61} = mode;
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let Inst{60-59} = size;
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let Inst{63-61} = BPF_MEM.Value;
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let Inst{60-59} = SizeOp.Value;
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let Inst{51-48} = addr{19-16}; // base reg
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let Inst{55-52} = src;
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let Inst{47-32} = addr{15-0}; // offset
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let mode = 3; // BPF_MEM
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let size = SizeOp;
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let BPFClass = 3; // BPF_STX
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let BPFClass = BPF_STX;
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}
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class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
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class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
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: STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
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def STW : STOREi64<0x0, "u32", truncstorei32>;
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def STH : STOREi64<0x1, "u16", truncstorei16>;
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def STB : STOREi64<0x2, "u8", truncstorei8>;
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def STD : STOREi64<0x3, "u64", store>;
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||||
def STW : STOREi64<BPF_W, "u32", truncstorei32>;
|
||||
def STH : STOREi64<BPF_H, "u16", truncstorei16>;
|
||||
def STB : STOREi64<BPF_B, "u8", truncstorei8>;
|
||||
def STD : STOREi64<BPF_DW, "u64", store>;
|
||||
|
||||
// LOAD instructions
|
||||
class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
|
||||
class LOAD<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
|
||||
: InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
|
||||
"$dst = *("#OpcodeStr#" *)($addr)", Pattern> {
|
||||
bits<3> mode;
|
||||
bits<2> size;
|
||||
bits<4> dst;
|
||||
bits<20> addr;
|
||||
|
||||
let Inst{63-61} = mode;
|
||||
let Inst{60-59} = size;
|
||||
let Inst{63-61} = BPF_MEM.Value;
|
||||
let Inst{60-59} = SizeOp.Value;
|
||||
let Inst{51-48} = dst;
|
||||
let Inst{55-52} = addr{19-16};
|
||||
let Inst{47-32} = addr{15-0};
|
||||
|
||||
let mode = 3; // BPF_MEM
|
||||
let size = SizeOp;
|
||||
let BPFClass = 1; // BPF_LDX
|
||||
let BPFClass = BPF_LDX;
|
||||
}
|
||||
|
||||
class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
|
||||
class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
|
||||
: LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
|
||||
|
||||
def LDW : LOADi64<0x0, "u32", zextloadi32>;
|
||||
def LDH : LOADi64<0x1, "u16", zextloadi16>;
|
||||
def LDB : LOADi64<0x2, "u8", zextloadi8>;
|
||||
def LDD : LOADi64<0x3, "u64", load>;
|
||||
def LDW : LOADi64<BPF_W, "u32", zextloadi32>;
|
||||
def LDH : LOADi64<BPF_H, "u16", zextloadi16>;
|
||||
def LDB : LOADi64<BPF_B, "u8", zextloadi8>;
|
||||
def LDD : LOADi64<BPF_DW, "u64", load>;
|
||||
|
||||
class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern>
|
||||
class BRANCH<BPFJumpOp Opc, string OpcodeStr, list<dag> Pattern>
|
||||
: InstBPF<(outs), (ins brtarget:$BrDst),
|
||||
!strconcat(OpcodeStr, " $BrDst"), Pattern> {
|
||||
bits<4> op;
|
||||
bits<16> BrDst;
|
||||
bits<1> BPFSrc;
|
||||
|
||||
let Inst{63-60} = op;
|
||||
let Inst{59} = BPFSrc;
|
||||
let Inst{63-60} = Opc.Value;
|
||||
let Inst{59} = BPF_K.Value;
|
||||
let Inst{47-32} = BrDst;
|
||||
|
||||
let op = Opc;
|
||||
let BPFSrc = 0;
|
||||
let BPFClass = 5; // BPF_JMP
|
||||
let BPFClass = BPF_JMP;
|
||||
}
|
||||
|
||||
class CALL<string OpcodeStr>
|
||||
: InstBPF<(outs), (ins calltarget:$BrDst),
|
||||
!strconcat(OpcodeStr, " $BrDst"), []> {
|
||||
bits<4> op;
|
||||
bits<32> BrDst;
|
||||
bits<1> BPFSrc;
|
||||
|
||||
let Inst{63-60} = op;
|
||||
let Inst{59} = BPFSrc;
|
||||
let Inst{63-60} = BPF_CALL.Value;
|
||||
let Inst{59} = BPF_K.Value;
|
||||
let Inst{31-0} = BrDst;
|
||||
|
||||
let op = 8; // BPF_CALL
|
||||
let BPFSrc = 0;
|
||||
let BPFClass = 5; // BPF_JMP
|
||||
let BPFClass = BPF_JMP;
|
||||
}
|
||||
|
||||
// Jump always
|
||||
let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
|
||||
def JMP : BRANCH<0x0, "goto", [(br bb:$BrDst)]>;
|
||||
def JMP : BRANCH<BPF_JA, "goto", [(br bb:$BrDst)]>;
|
||||
}
|
||||
|
||||
// Jump and link
|
||||
|
|
@ -418,21 +370,12 @@ class NOP_I<string OpcodeStr>
|
|||
: InstBPF<(outs), (ins i32imm:$imm),
|
||||
!strconcat(OpcodeStr, "\t$imm"), []> {
|
||||
// mov r0, r0 == nop
|
||||
bits<4> op;
|
||||
bits<1> BPFSrc;
|
||||
bits<4> dst;
|
||||
bits<4> src;
|
||||
let Inst{63-60} = BPF_MOV.Value;
|
||||
let Inst{59} = BPF_X.Value;
|
||||
let Inst{55-52} = 0;
|
||||
let Inst{51-48} = 0;
|
||||
|
||||
let Inst{63-60} = op;
|
||||
let Inst{59} = BPFSrc;
|
||||
let Inst{55-52} = src;
|
||||
let Inst{51-48} = dst;
|
||||
|
||||
let op = 0xb; // BPF_MOV
|
||||
let BPFSrc = 1; // BPF_X
|
||||
let BPFClass = 7; // BPF_ALU64
|
||||
let src = 0; // R0
|
||||
let dst = 0; // R0
|
||||
let BPFClass = BPF_ALU64;
|
||||
}
|
||||
|
||||
let hasSideEffects = 0 in
|
||||
|
|
@ -441,14 +384,11 @@ let hasSideEffects = 0 in
|
|||
class RET<string OpcodeStr>
|
||||
: InstBPF<(outs), (ins),
|
||||
!strconcat(OpcodeStr, ""), [(BPFretflag)]> {
|
||||
bits<4> op;
|
||||
|
||||
let Inst{63-60} = op;
|
||||
let Inst{63-60} = BPF_EXIT.Value;
|
||||
let Inst{59} = 0;
|
||||
let Inst{31-0} = 0;
|
||||
|
||||
let op = 9; // BPF_EXIT
|
||||
let BPFClass = 5; // BPF_JMP
|
||||
let BPFClass = BPF_JMP;
|
||||
}
|
||||
|
||||
let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
|
||||
|
|
@ -497,29 +437,25 @@ def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>;
|
|||
def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>;
|
||||
|
||||
// Atomics
|
||||
class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
|
||||
class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
|
||||
: InstBPF<(outs GPR:$dst), (ins MEMri:$addr, GPR:$val),
|
||||
"lock *("#OpcodeStr#" *)($addr) += $val",
|
||||
[(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
|
||||
bits<3> mode;
|
||||
bits<2> size;
|
||||
bits<4> dst;
|
||||
bits<20> addr;
|
||||
|
||||
let Inst{63-61} = mode;
|
||||
let Inst{60-59} = size;
|
||||
let Inst{63-61} = BPF_XADD.Value;
|
||||
let Inst{60-59} = SizeOp.Value;
|
||||
let Inst{51-48} = addr{19-16}; // base reg
|
||||
let Inst{55-52} = dst;
|
||||
let Inst{47-32} = addr{15-0}; // offset
|
||||
|
||||
let mode = 6; // BPF_XADD
|
||||
let size = SizeOp;
|
||||
let BPFClass = 3; // BPF_STX
|
||||
let BPFClass = BPF_STX;
|
||||
}
|
||||
|
||||
let Constraints = "$dst = $val" in {
|
||||
def XADD32 : XADD<0, "u32", atomic_load_add_32>;
|
||||
def XADD64 : XADD<3, "u64", atomic_load_add_64>;
|
||||
def XADD32 : XADD<BPF_W, "u32", atomic_load_add_32>;
|
||||
def XADD64 : XADD<BPF_DW, "u64", atomic_load_add_64>;
|
||||
// undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
|
||||
// undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
|
||||
}
|
||||
|
|
@ -529,19 +465,15 @@ class BSWAP<bits<32> SizeOp, string OpcodeStr, list<dag> Pattern>
|
|||
: InstBPF<(outs GPR:$dst), (ins GPR:$src),
|
||||
!strconcat(OpcodeStr, "\t$dst"),
|
||||
Pattern> {
|
||||
bits<4> op;
|
||||
bits<1> BPFSrc;
|
||||
bits<4> dst;
|
||||
bits<32> imm;
|
||||
|
||||
let Inst{63-60} = op;
|
||||
let Inst{59} = BPFSrc;
|
||||
let Inst{63-60} = BPF_END.Value;
|
||||
let Inst{59} = BPF_TO_BE.Value; // (TODO: use BPF_TO_LE for big-endian target)
|
||||
let Inst{51-48} = dst;
|
||||
let Inst{31-0} = imm;
|
||||
|
||||
let op = 0xd; // BPF_END
|
||||
let BPFSrc = 1; // BPF_TO_BE (TODO: use BPF_TO_LE for big-endian target)
|
||||
let BPFClass = 4; // BPF_ALU
|
||||
let BPFClass = BPF_ALU;
|
||||
let imm = SizeOp;
|
||||
}
|
||||
|
||||
|
|
@ -553,45 +485,37 @@ def BSWAP64 : BSWAP<64, "bswap64", [(set GPR:$dst, (bswap GPR:$src))]>;
|
|||
|
||||
let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
|
||||
hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
|
||||
class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
|
||||
class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
|
||||
: InstBPF<(outs), (ins GPR:$skb, i64imm:$imm),
|
||||
"r0 = *("#OpcodeStr#" *)skb[$imm]",
|
||||
[(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
|
||||
bits<3> mode;
|
||||
bits<2> size;
|
||||
bits<32> imm;
|
||||
|
||||
let Inst{63-61} = mode;
|
||||
let Inst{60-59} = size;
|
||||
let Inst{63-61} = BPF_ABS.Value;
|
||||
let Inst{60-59} = SizeOp.Value;
|
||||
let Inst{31-0} = imm;
|
||||
|
||||
let mode = 1; // BPF_ABS
|
||||
let size = SizeOp;
|
||||
let BPFClass = 0; // BPF_LD
|
||||
let BPFClass = BPF_LD;
|
||||
}
|
||||
|
||||
class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
|
||||
class LOAD_IND<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
|
||||
: InstBPF<(outs), (ins GPR:$skb, GPR:$val),
|
||||
"r0 = *("#OpcodeStr#" *)skb[$val]",
|
||||
[(set R0, (OpNode GPR:$skb, GPR:$val))]> {
|
||||
bits<3> mode;
|
||||
bits<2> size;
|
||||
bits<4> val;
|
||||
|
||||
let Inst{63-61} = mode;
|
||||
let Inst{60-59} = size;
|
||||
let Inst{63-61} = BPF_IND.Value;
|
||||
let Inst{60-59} = SizeOp.Value;
|
||||
let Inst{55-52} = val;
|
||||
|
||||
let mode = 2; // BPF_IND
|
||||
let size = SizeOp;
|
||||
let BPFClass = 0; // BPF_LD
|
||||
let BPFClass = BPF_LD;
|
||||
}
|
||||
}
|
||||
|
||||
def LD_ABS_B : LOAD_ABS<2, "u8", int_bpf_load_byte>;
|
||||
def LD_ABS_H : LOAD_ABS<1, "u16", int_bpf_load_half>;
|
||||
def LD_ABS_W : LOAD_ABS<0, "u32", int_bpf_load_word>;
|
||||
def LD_ABS_B : LOAD_ABS<BPF_B, "u8", int_bpf_load_byte>;
|
||||
def LD_ABS_H : LOAD_ABS<BPF_H, "u16", int_bpf_load_half>;
|
||||
def LD_ABS_W : LOAD_ABS<BPF_W, "u32", int_bpf_load_word>;
|
||||
|
||||
def LD_IND_B : LOAD_IND<2, "u8", int_bpf_load_byte>;
|
||||
def LD_IND_H : LOAD_IND<1, "u16", int_bpf_load_half>;
|
||||
def LD_IND_W : LOAD_IND<0, "u32", int_bpf_load_word>;
|
||||
def LD_IND_B : LOAD_IND<BPF_B, "u8", int_bpf_load_byte>;
|
||||
def LD_IND_H : LOAD_IND<BPF_H, "u16", int_bpf_load_half>;
|
||||
def LD_IND_W : LOAD_IND<BPF_W, "u32", int_bpf_load_word>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue