forked from OSchip/llvm-project
Add a RegisterTuples class to Target.td and TableGen.
A RegisterTuples instance is used to synthesize super-registers by
zipping together lists of sub-registers. This is useful for generating
pseudo-registers representing register sequence constraints like 'two
consecutive GPRs', or 'an even-odd pair of floating point registers'.
The RegisterTuples def can be used in register set operations when
building register classes. That is the only way of accessing the
synthesized super-registers.
For example, the ARM QQ register class of pseudo-registers could have
been formed like this:
// Form pairs Q0_Q1, Q2_Q3, ...
def QQPairs : RegisterTuples<[qsub_0, qsub_1],
[(decimate QPR, 2),
(decimate (shl QPR, 1), 2)]>;
def QQ : RegisterClass<..., (add QQPairs)>;
Similarly, pseudo-registers representing '3 consecutive D-regs with
wraparound' look like:
// Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1.
def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2],
[(rotl DPR, 0),
(rotl DPR, 1),
(rotl DPR, 2)]>;
TableGen automatically computes aliasing information for the synthesized
registers.
Register tuples are still somewhat experimental. We still need to see
how they interact with MC.
llvm-svn: 133407
This commit is contained in:
Jakob Stoklund Olesen
parent
dceb0cf3f3
commit
3bd1b65ed3
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@ -184,6 +184,43 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
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def sequence;
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def decimate;
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// RegisterTuples - Automatically generate super-registers by forming tuples of
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// sub-registers. This is useful for modeling register sequence constraints
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// with pseudo-registers that are larger than the architectural registers.
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//
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// The sub-register lists are zipped together:
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//
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// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
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//
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// Generates the same registers as:
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//
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// let SubRegIndices = [sube, subo] in {
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// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
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// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
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// }
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//
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// The generated pseudo-registers inherit super-classes and fields from their
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// first sub-register. Most fields from the Register class are inferred, and
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// the AsmName and Dwarf numbers are cleared.
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//
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// RegisterTuples instances can be used in other set operations to form
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// register classes and so on. This is the only way of using the generated
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// registers.
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class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
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// SubRegs - N lists of registers to be zipped up. Super-registers are
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// synthesized from the first element of each SubRegs list, the second
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// element and so on.
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list<dag> SubRegs = Regs;
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// SubRegIndices - N SubRegIndex instances. This provides the names of the
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// sub-registers in the synthesized super-registers.
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list<SubRegIndex> SubRegIndices = Indices;
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// Compose sub-register indices like in a normal Register.
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list<dag> CompositeIndices = [];
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}
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//===----------------------------------------------------------------------===//
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// DwarfRegNum - This class provides a mapping of the llvm register enumeration
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// to the register numbering used by gcc and gdb. These values are used by a
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@ -150,6 +150,104 @@ CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const {
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}
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}
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//===----------------------------------------------------------------------===//
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// RegisterTuples
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//===----------------------------------------------------------------------===//
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// A RegisterTuples def is used to generate pseudo-registers from lists of
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// sub-registers. We provide a SetTheory expander class that returns the new
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// registers.
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namespace {
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struct TupleExpander : SetTheory::Expander {
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void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
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std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
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unsigned Dim = Indices.size();
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ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
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if (Dim != SubRegs->getSize())
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throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
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if (Dim < 2)
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throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
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// Evaluate the sub-register lists to be zipped.
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unsigned Length = ~0u;
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SmallVector<SetTheory::RecSet, 4> Lists(Dim);
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for (unsigned i = 0; i != Dim; ++i) {
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ST.evaluate(SubRegs->getElement(i), Lists[i]);
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Length = std::min(Length, unsigned(Lists[i].size()));
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}
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if (Length == 0)
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return;
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// Precompute some types.
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Record *RegisterCl = Def->getRecords().getClass("Register");
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RecTy *RegisterRecTy = new RecordRecTy(RegisterCl);
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StringInit *BlankName = new StringInit("");
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// Zip them up.
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for (unsigned n = 0; n != Length; ++n) {
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std::string Name;
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Record *Proto = Lists[0][n];
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std::vector<Init*> Tuple;
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unsigned CostPerUse = 0;
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for (unsigned i = 0; i != Dim; ++i) {
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Record *Reg = Lists[i][n];
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if (i) Name += '_';
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Name += Reg->getName();
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Tuple.push_back(new DefInit(Reg));
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CostPerUse = std::max(CostPerUse,
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unsigned(Reg->getValueAsInt("CostPerUse")));
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}
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// Create a new Record representing the synthesized register. This record
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// is only for consumption by CodeGenRegister, it is not added to the
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// RecordKeeper.
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Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
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Elts.insert(NewReg);
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// Copy Proto super-classes.
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for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
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NewReg->addSuperClass(Proto->getSuperClasses()[i]);
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// Copy Proto fields.
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for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
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RecordVal RV = Proto->getValues()[i];
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// Replace the sub-register list with Tuple.
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if (RV.getName() == "SubRegs")
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RV.setValue(new ListInit(Tuple, RegisterRecTy));
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// Provide a blank AsmName. MC hacks are required anyway.
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if (RV.getName() == "AsmName")
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RV.setValue(BlankName);
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// CostPerUse is aggregated from all Tuple members.
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if (RV.getName() == "CostPerUse")
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RV.setValue(new IntInit(CostPerUse));
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// Copy fields from the RegisterTuples def.
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if (RV.getName() == "SubRegIndices" ||
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RV.getName() == "CompositeIndices") {
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NewReg->addValue(*Def->getValue(RV.getName()));
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continue;
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}
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// Some fields get their default uninitialized value.
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if (RV.getName() == "DwarfNumbers" ||
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RV.getName() == "DwarfAlias" ||
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RV.getName() == "Aliases") {
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NewReg->addValue(*RegisterCl->getValue(RV.getName()));
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continue;
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}
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// Everything else is copied from Proto.
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NewReg->addValue(RV);
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}
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}
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}
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};
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}
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//===----------------------------------------------------------------------===//
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// CodeGenRegisterClass
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//===----------------------------------------------------------------------===//
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@ -258,8 +356,9 @@ const std::string &CodeGenRegisterClass::getName() const {
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//===----------------------------------------------------------------------===//
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CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
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// Configure register Sets to understand register classes.
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// Configure register Sets to understand register classes and tuples.
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Sets.addFieldExpander("RegisterClass", "MemberList");
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Sets.addExpander("RegisterTuples", new TupleExpander());
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// Read in the user-defined (named) sub-register indices.
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// More indices will be synthesized later.
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@ -275,6 +374,15 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
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for (unsigned i = 0, e = Regs.size(); i != e; ++i)
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getReg(Regs[i]);
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// Expand tuples and number the new registers.
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std::vector<Record*> Tups =
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Records.getAllDerivedDefinitions("RegisterTuples");
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for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
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const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
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for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
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getReg((*TupRegs)[j]);
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}
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// Read in register class definitions.
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std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
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if (RCs.empty())
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