forked from OSchip/llvm-project
[AMDGPU] Use v3f32 type in image instructions
This should lower the amount of used registers for gfx9. I updated some of the changed tests with the update script because changing them by hand is tedious. Differential Revision: https://reviews.llvm.org/D73884
This commit is contained in:
Sebastian Neubauer
parent
60f161eb62
commit
3bc7ffdaab
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@ -5119,6 +5119,9 @@ static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
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} else if (Elts.size() == 2) {
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Type = MVT::v2f32;
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NumElts = 2;
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} else if (Elts.size() == 3) {
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Type = MVT::v3f32;
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NumElts = 3;
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} else if (Elts.size() <= 4) {
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Type = MVT::v4f32;
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NumElts = 4;
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@ -35,8 +35,8 @@ main_body:
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}
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; GCN-LABEL: {{^}}image_load_mip_v4f16:
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; UNPACKED: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm d16{{$}}
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; PACKED: image_load_mip v[0:1], v[0:3], s[0:7] dmask:0xf unorm d16{{$}}
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; UNPACKED: image_load_mip v[0:3], v[0:2], s[0:7] dmask:0xf unorm d16{{$}}
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; PACKED: image_load_mip v[0:1], v[0:2], s[0:7] dmask:0xf unorm d16{{$}}
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; GFX10: image_load_mip v[0:1], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm d16{{$}}
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define amdgpu_ps <2 x float> @image_load_mip_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %mip) {
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main_body:
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@ -46,8 +46,8 @@ main_body:
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}
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; GCN-LABEL: {{^}}image_load_3d_v2f16:
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; UNPACKED: image_load v[0:1], v[0:3], s[0:7] dmask:0x3 unorm d16{{$}}
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; PACKED: image_load v0, v[0:3], s[0:7] dmask:0x3 unorm d16{{$}}
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; UNPACKED: image_load v[0:1], v[0:2], s[0:7] dmask:0x3 unorm d16{{$}}
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; PACKED: image_load v0, v[0:2], s[0:7] dmask:0x3 unorm d16{{$}}
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; GFX10: image_load v0, v[0:2], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm d16{{$}}
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define amdgpu_ps float @image_load_3d_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {
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main_body:
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File diff suppressed because it is too large
Load Diff
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@ -41,7 +41,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_cl_2d:
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; GCN: image_gather4_c_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 a16{{$}}
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; GCN: image_gather4_c_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16{{$}}
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define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %clamp) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -57,7 +57,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_b_2d:
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; GCN: image_gather4_c_b v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 a16{{$}}
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; GCN: image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16{{$}}
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define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32.f16(i32 1, float %bias, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -65,7 +65,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_b_cl_2d:
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; GCN: image_gather4_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 a16{{$}}
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; GCN: image_gather4_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16{{$}}
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define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t, half %clamp) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f32.f16(i32 1, float %bias, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -89,7 +89,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_l_2d:
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; GCN: image_gather4_c_l v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 a16{{$}}
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; GCN: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16{{$}}
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define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %lod) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -4,8 +4,8 @@
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; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX10 %s
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; GCN-LABEL: {{^}}image_gather4_b_2d_v4f16:
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; UNPACKED: image_gather4_b v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x4 d16{{$}}
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; PACKED: image_gather4_b v[0:1], v[0:3], s[0:7], s[8:11] dmask:0x4 d16{{$}}
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; UNPACKED: image_gather4_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x4 d16{{$}}
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; PACKED: image_gather4_b v[0:1], v[0:2], s[0:7], s[8:11] dmask:0x4 d16{{$}}
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; GFX10: image_gather4_b v[0:1], v[0:2], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D d16{{$}}
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define amdgpu_ps <2 x float> @image_gather4_b_2d_v4f16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t) {
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main_body:
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@ -12,7 +12,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_cube:
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; GFX6789: image_gather4 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 da{{$}}
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; GFX6789: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 da{{$}}
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; GFX10: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ;
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define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %face) {
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main_body:
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@ -21,7 +21,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_2darray:
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; GFX6789: image_gather4 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 da{{$}}
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; GFX6789: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 da{{$}}
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; GFX10: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY ;
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define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %slice) {
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main_body:
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@ -30,7 +30,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_2d:
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; GFX6789: image_gather4_c v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX6789: image_gather4_c v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX10: image_gather4_c v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
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define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
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main_body:
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@ -39,7 +39,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_cl_2d:
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; GFX6789: image_gather4_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX6789: image_gather4_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX10: image_gather4_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
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define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %clamp) {
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main_body:
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@ -57,7 +57,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_b_2d:
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; GFX6789: image_gather4_b v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX6789: image_gather4_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX10: image_gather4_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
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define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t) {
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main_body:
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@ -93,7 +93,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_l_2d:
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; GFX6789: image_gather4_l v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX6789: image_gather4_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX10: image_gather4_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
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define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {
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main_body:
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@ -120,7 +120,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_lz_2d:
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; GFX6789: image_gather4_c_lz v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX6789: image_gather4_c_lz v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX10: image_gather4_c_lz v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
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define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
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main_body:
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@ -2,7 +2,7 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; GCN-LABEL: {{^}}gather4_o_2d:
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; GCN: image_gather4_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
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; GCN: image_gather4_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
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define amdgpu_ps <4 x float> @gather4_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -82,7 +82,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_lz_o_2d:
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; GCN: image_gather4_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1{{$}}
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; GCN: image_gather4_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1{{$}}
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define amdgpu_ps <4 x float> @gather4_lz_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -15,7 +15,7 @@ main_body:
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; GCN-LABEL: {{^}}sample_3d:
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; NONSA: v_mov_b32_e32 v3, v0
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; NONSA: image_sample v[0:3], v[1:4],
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; NONSA: image_sample v[0:3], v[1:3],
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; NSA: image_sample v[0:3], [v1, v2, v0],
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define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %r, float %s, float %t) {
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main_body:
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@ -70,7 +70,7 @@ main_body:
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; GCN-LABEL: {{^}}sample_contig_contig:
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; GCN: image_sample_c_l v0, v[0:7],
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; NSA: image_sample v1, v[5:7],
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; NONSA: image_sample v1, v[5:8],
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; NONSA: image_sample v1, v[5:7],
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define amdgpu_ps <2 x float> @sample_contig_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %s2, float %t2, float %r2) {
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main_body:
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%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -1,374 +1,624 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; GCN: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16{{$}}
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define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {
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; GCN-LABEL: sample_1d:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b64 s[12:13], exec
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; GCN-NEXT: s_wqm_b64 exec, exec
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; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
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; GCN-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: ; return to shader part epilog
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16(i32 15, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}sample_2d:
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; GCN: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16{{$}}
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define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
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; GCN-LABEL: sample_2d:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b64 s[12:13], exec
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; GCN-NEXT: s_wqm_b64 exec, exec
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; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
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; GCN-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: ; return to shader part epilog
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f16(i32 15, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}sample_3d:
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; GCN: image_sample v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
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define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %r) {
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; GCN-LABEL: sample_3d:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b64 s[12:13], exec
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; GCN-NEXT: s_wqm_b64 exec, exec
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; GCN-NEXT: v_mov_b32_e32 v1, v2
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; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f16(i32 15, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cube:
|
||||
; GCN: image_sample v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16 da{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {
|
||||
; GCN-LABEL: sample_cube:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, v2
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16 da
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f16(i32 15, half %s, half %t, half %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_1darray:
|
||||
; GCN: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16 da{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %slice) {
|
||||
; GCN-LABEL: sample_1darray:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16 da
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f16(i32 15, half %s, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_2darray:
|
||||
; GCN: image_sample v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16 da{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {
|
||||
; GCN-LABEL: sample_2darray:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, v2
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16 da
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f16(i32 15, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_1d:
|
||||
; GCN: image_sample_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s) {
|
||||
; GCN-LABEL: sample_c_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f16(i32 15, float %zcompare, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_2d:
|
||||
; GCN: image_sample_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {
|
||||
; GCN-LABEL: sample_c_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cl_1d:
|
||||
; GCN: image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %clamp) {
|
||||
; GCN-LABEL: sample_cl_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cl.1d.v4f32.f16(i32 15, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cl_2d:
|
||||
; GCN: image_sample_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %clamp) {
|
||||
; GCN-LABEL: sample_cl_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, v2
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cl.2d.v4f32.f16(i32 15, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_cl_1d:
|
||||
; GCN: image_sample_c_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %clamp) {
|
||||
; GCN-LABEL: sample_c_cl_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_c_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f16(i32 15, float %zcompare, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_cl_2d:
|
||||
; GCN: image_sample_c_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %clamp) {
|
||||
; GCN-LABEL: sample_c_cl_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v3
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_c_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_b_1d:
|
||||
; GCN: image_sample_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s) {
|
||||
; GCN-LABEL: sample_b_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f16(i32 15, float %bias, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_b_2d:
|
||||
; GCN: image_sample_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t) {
|
||||
; GCN-LABEL: sample_b_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32.f16(i32 15, float %bias, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_b_1d:
|
||||
; GCN: image_sample_c_b v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s) {
|
||||
; GCN-LABEL: sample_c_b_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.f16(i32 15, float %bias, float %zcompare, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_b_2d:
|
||||
; GCN: image_sample_c_b v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t) {
|
||||
; GCN-LABEL: sample_c_b_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32.f16(i32 15, float %bias, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_b_cl_1d:
|
||||
; GCN: image_sample_b_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %clamp) {
|
||||
; GCN-LABEL: sample_b_cl_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_b_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f32.f16(i32 15, float %bias, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_b_cl_2d:
|
||||
; GCN: image_sample_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t, half %clamp) {
|
||||
; GCN-LABEL: sample_b_cl_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v3
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f32.f16(i32 15, float %bias, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_b_cl_1d:
|
||||
; GCN: image_sample_c_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %clamp) {
|
||||
; GCN-LABEL: sample_c_b_cl_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_c_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f32.f16(i32 15, float %bias, float %zcompare, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_b_cl_2d:
|
||||
; GCN: image_sample_c_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t, half %clamp) {
|
||||
; GCN-LABEL: sample_c_b_cl_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GCN-NEXT: s_wqm_b64 exec, exec
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v4
|
||||
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GCN-NEXT: image_sample_c_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f32.f16(i32 15, float %bias, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_d_1d:
|
||||
; GCN: image_sample_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s) {
|
||||
; GCN-LABEL: sample_d_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f16(i32 15, half %dsdh, half %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_d_2d:
|
||||
; GCN: image_sample_d v[0:3], v[1:4], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
|
||||
; GCN-LABEL: sample_d_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v4
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, v0
|
||||
; GCN-NEXT: image_sample_d v[0:3], v[1:3], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABAL: {{^}}sample_d_3d:
|
||||
; GCN: image_sample_d v[0:3], v[2:9], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r) {
|
||||
; GCN-LABEL: sample_d_3d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, v3
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v7, v8
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GCN-NEXT: image_sample_d v[0:3], v[2:9], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_d_1d:
|
||||
; GCN: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {
|
||||
; GCN-LABEL: sample_c_d_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_d_2d:
|
||||
; GCN: image_sample_c_d v[0:3], v[1:4], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
|
||||
; GCN-LABEL: sample_c_d_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, v5
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, v0
|
||||
; GCN-NEXT: image_sample_c_d v[0:3], v[1:4], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_d_cl_1d:
|
||||
; GCN: image_sample_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {
|
||||
; GCN-LABEL: sample_d_cl_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f16(i32 15, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_d_cl_2d:
|
||||
; GCN: image_sample_d_cl v[0:3], v[2:5], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
|
||||
; GCN-LABEL: sample_d_cl_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, v6
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GCN-NEXT: image_sample_d_cl v[0:3], v[2:5], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_d_cl_1d:
|
||||
; GCN: image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {
|
||||
; GCN-LABEL: sample_c_d_cl_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_d_cl_2d:
|
||||
; GCN: image_sample_c_d_cl v[0:3], v[2:9], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
|
||||
; GCN-LABEL: sample_c_d_cl_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, v3
|
||||
; GCN-NEXT: v_mov_b32_e32 v6, v7
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GCN-NEXT: image_sample_c_d_cl v[0:3], v[2:9], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cd_1d:
|
||||
; GCN: image_sample_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s) {
|
||||
; GCN-LABEL: sample_cd_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f16(i32 15, half %dsdh, half %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cd_2d:
|
||||
; GCN: image_sample_cd v[0:3], v[1:4], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
|
||||
; GCN-LABEL: sample_cd_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v4
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, v0
|
||||
; GCN-NEXT: image_sample_cd v[0:3], v[1:3], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_cd_1d:
|
||||
; GCN: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {
|
||||
; GCN-LABEL: sample_c_cd_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dsdv, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_cd_2d:
|
||||
; GCN: image_sample_c_cd v[0:3], v[1:4], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
|
||||
; GCN-LABEL: sample_c_cd_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, v5
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, v0
|
||||
; GCN-NEXT: image_sample_c_cd v[0:3], v[1:4], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cd_cl_1d:
|
||||
; GCN: image_sample_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {
|
||||
; GCN-LABEL: sample_cd_cl_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f16(i32 15, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cd_cl_2d:
|
||||
; GCN: image_sample_cd_cl v[0:3], v[2:5], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
|
||||
; GCN-LABEL: sample_cd_cl_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, v6
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GCN-NEXT: image_sample_cd_cl v[0:3], v[2:5], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_cd_cl_1d:
|
||||
; GCN: image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {
|
||||
; GCN-LABEL: sample_c_cd_cl_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_cd_cl_2d:
|
||||
; GCN: image_sample_c_cd_cl v[0:3], v[2:9], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
|
||||
; GCN-LABEL: sample_c_cd_cl_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, v3
|
||||
; GCN-NEXT: v_mov_b32_e32 v6, v7
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GCN-NEXT: image_sample_c_cd_cl v[0:3], v[2:9], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_l_1d:
|
||||
; GCN: image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %lod) {
|
||||
; GCN-LABEL: sample_l_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f16(i32 15, half %s, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_l_2d:
|
||||
; GCN: image_sample_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %lod) {
|
||||
; GCN-LABEL: sample_l_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, v2
|
||||
; GCN-NEXT: image_sample_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f16(i32 15, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_l_1d:
|
||||
; GCN: image_sample_c_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %lod) {
|
||||
; GCN-LABEL: sample_c_l_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_c_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f16(i32 15, float %zcompare, half %s, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_l_2d:
|
||||
; GCN: image_sample_c_l v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %lod) {
|
||||
; GCN-LABEL: sample_c_l_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v3
|
||||
; GCN-NEXT: image_sample_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_lz_1d:
|
||||
; GCN: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {
|
||||
; GCN-LABEL: sample_lz_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f16(i32 15, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_lz_2d:
|
||||
; GCN: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
|
||||
; GCN-LABEL: sample_lz_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f16(i32 15, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_lz_1d:
|
||||
; GCN: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s) {
|
||||
; GCN-LABEL: sample_c_lz_1d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f16(i32 15, float %zcompare, half %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_lz_2d:
|
||||
; GCN: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {
|
||||
; GCN-LABEL: sample_c_lz_2d:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_d_o_2darray_V1:
|
||||
; GCN: image_sample_c_d_o v0, v[2:9], s[0:7], s[8:11] dmask:0x4 a16 da{{$}}
|
||||
define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {
|
||||
; GCN-LABEL: sample_c_d_o_2darray_V1:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, v4
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v7, v8
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GCN-NEXT: image_sample_c_d_o v0, v[2:9], s[0:7], s[8:11] dmask:0x4 a16 da
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f16(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret float %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_d_o_2darray_V2:
|
||||
; GCN: image_sample_c_d_o v[0:1], v[2:9], s[0:7], s[8:11] dmask:0x6 a16 da{{$}}
|
||||
define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {
|
||||
; GCN-LABEL: sample_c_d_o_2darray_V2:
|
||||
; GCN: ; %bb.0: ; %main_body
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, v4
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v7, v8
|
||||
; GCN-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GCN-NEXT: image_sample_c_d_o v[0:1], v[2:9], s[0:7], s[8:11] dmask:0x6 a16 da
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret <2 x float> %v
|
||||
|
|
|
|||
|
|
@ -1,22 +1,120 @@
|
|||
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=GCN,UNPACKED,GFX89 %s
|
||||
; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=GCN,PACKED,GFX81,GFX89 %s
|
||||
; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GCN,PACKED,GFX9,GFX89 %s
|
||||
; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX10 %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=TONGA %s
|
||||
; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=GFX81 %s
|
||||
; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GFX9 %s
|
||||
; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10 %s
|
||||
|
||||
; GCN-LABEL: {{^}}image_sample_2d_f16:
|
||||
; GFX89: image_sample v0, v[0:1], s[0:7], s[8:11] dmask:0x1 d16{{$}}
|
||||
; GFX10: image_sample v0, v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D d16{{$}}
|
||||
define amdgpu_ps half @image_sample_2d_f16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
|
||||
; TONGA-LABEL: image_sample_2d_f16:
|
||||
; TONGA: ; %bb.0: ; %main_body
|
||||
; TONGA-NEXT: s_mov_b64 s[12:13], exec
|
||||
; TONGA-NEXT: s_wqm_b64 exec, exec
|
||||
; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; TONGA-NEXT: image_sample v0, v[0:1], s[0:7], s[8:11] dmask:0x1 d16
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(0)
|
||||
; TONGA-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX81-LABEL: image_sample_2d_f16:
|
||||
; GFX81: ; %bb.0: ; %main_body
|
||||
; GFX81-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GFX81-NEXT: s_wqm_b64 exec, exec
|
||||
; GFX81-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GFX81-NEXT: s_nop 0
|
||||
; GFX81-NEXT: image_sample v0, v[0:1], s[0:7], s[8:11] dmask:0x1 d16
|
||||
; GFX81-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX81-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX9-LABEL: image_sample_2d_f16:
|
||||
; GFX9: ; %bb.0: ; %main_body
|
||||
; GFX9-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GFX9-NEXT: s_wqm_b64 exec, exec
|
||||
; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GFX9-NEXT: image_sample v0, v[0:1], s[0:7], s[8:11] dmask:0x1 d16
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: image_sample_2d_f16:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: s_mov_b32 s12, exec_lo
|
||||
; GFX10-NEXT: ; implicit-def: $vcc_hi
|
||||
; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
|
||||
; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
||||
; GFX10-NEXT: image_sample v0, v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%tex = call half @llvm.amdgcn.image.sample.2d.f16.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
|
||||
ret half %tex
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_sample_2d_f16_tfe:
|
||||
; GCN: v_mov_b32_e32 v{{[0-9]+}}, 0
|
||||
; PACKED: image_sample v[2:3], v[0:1], s[0:7], s[8:11] dmask:0x1 tfe d16{{$}}
|
||||
; UNPACKED: image_sample v[2:3], v[0:1], s[0:7], s[8:11] dmask:0x1 tfe d16{{$}}
|
||||
define amdgpu_ps half @image_sample_2d_f16_tfe(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, i32 addrspace(1)* inreg %out) {
|
||||
; TONGA-LABEL: image_sample_2d_f16_tfe:
|
||||
; TONGA: ; %bb.0: ; %main_body
|
||||
; TONGA-NEXT: s_mov_b64 s[14:15], exec
|
||||
; TONGA-NEXT: s_wqm_b64 exec, exec
|
||||
; TONGA-NEXT: v_mov_b32_e32 v2, 0
|
||||
; TONGA-NEXT: v_mov_b32_e32 v4, s12
|
||||
; TONGA-NEXT: v_mov_b32_e32 v5, s13
|
||||
; TONGA-NEXT: v_mov_b32_e32 v3, v2
|
||||
; TONGA-NEXT: s_and_b64 exec, exec, s[14:15]
|
||||
; TONGA-NEXT: image_sample v[2:3], v[0:1], s[0:7], s[8:11] dmask:0x1 tfe d16
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(0)
|
||||
; TONGA-NEXT: v_mov_b32_e32 v0, v2
|
||||
; TONGA-NEXT: flat_store_dword v[4:5], v3
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; TONGA-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX81-LABEL: image_sample_2d_f16_tfe:
|
||||
; GFX81: ; %bb.0: ; %main_body
|
||||
; GFX81-NEXT: s_mov_b64 s[14:15], exec
|
||||
; GFX81-NEXT: s_wqm_b64 exec, exec
|
||||
; GFX81-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX81-NEXT: v_mov_b32_e32 v4, s12
|
||||
; GFX81-NEXT: v_mov_b32_e32 v5, s13
|
||||
; GFX81-NEXT: v_mov_b32_e32 v3, v2
|
||||
; GFX81-NEXT: s_and_b64 exec, exec, s[14:15]
|
||||
; GFX81-NEXT: s_nop 0
|
||||
; GFX81-NEXT: image_sample v[2:3], v[0:1], s[0:7], s[8:11] dmask:0x1 tfe d16
|
||||
; GFX81-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX81-NEXT: v_mov_b32_e32 v0, v2
|
||||
; GFX81-NEXT: s_nop 0
|
||||
; GFX81-NEXT: s_nop 0
|
||||
; GFX81-NEXT: flat_store_dword v[4:5], v3
|
||||
; GFX81-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; GFX81-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX9-LABEL: image_sample_2d_f16_tfe:
|
||||
; GFX9: ; %bb.0: ; %main_body
|
||||
; GFX9-NEXT: s_mov_b64 s[14:15], exec
|
||||
; GFX9-NEXT: s_wqm_b64 exec, exec
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, s12
|
||||
; GFX9-NEXT: v_mov_b32_e32 v5, s13
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, v2
|
||||
; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
|
||||
; GFX9-NEXT: image_sample v[2:3], v[0:1], s[0:7], s[8:11] dmask:0x1 tfe d16
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, v2
|
||||
; GFX9-NEXT: global_store_dword v[4:5], v3, off
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: image_sample_2d_f16_tfe:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: s_mov_b32 s14, exec_lo
|
||||
; GFX10-NEXT: ; implicit-def: $vcc_hi
|
||||
; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX10-NEXT: v_mov_b32_e32 v4, s12
|
||||
; GFX10-NEXT: v_mov_b32_e32 v5, s13
|
||||
; GFX10-NEXT: v_mov_b32_e32 v3, v2
|
||||
; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s14
|
||||
; GFX10-NEXT: image_sample v[2:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: v_mov_b32_e32 v0, v2
|
||||
; GFX10-NEXT: global_store_dword v[4:5], v3, off
|
||||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%tex = call {half,i32} @llvm.amdgcn.image.sample.2d.f16i32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)
|
||||
%tex.vec = extractvalue {half, i32} %tex, 0
|
||||
|
|
@ -25,22 +123,84 @@ main_body:
|
|||
ret half %tex.vec
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_sample_c_d_1d_v2f16:
|
||||
; UNPACKED: image_sample_c_d v[0:1], v[0:3], s[0:7], s[8:11] dmask:0x3 d16{{$}}
|
||||
; PACKED: image_sample_c_d v0, v[0:3], s[0:7], s[8:11] dmask:0x3 d16{{$}}
|
||||
; GFX10: image_sample_c_d v0, v[0:3], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D d16{{$}}
|
||||
define amdgpu_ps float @image_sample_c_d_1d_v2f16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, float %s) {
|
||||
; TONGA-LABEL: image_sample_c_d_1d_v2f16:
|
||||
; TONGA: ; %bb.0: ; %main_body
|
||||
; TONGA-NEXT: image_sample_c_d v[0:1], v[0:3], s[0:7], s[8:11] dmask:0x3 d16
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(0)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; TONGA-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; TONGA-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX81-LABEL: image_sample_c_d_1d_v2f16:
|
||||
; GFX81: ; %bb.0: ; %main_body
|
||||
; GFX81-NEXT: image_sample_c_d v0, v[0:3], s[0:7], s[8:11] dmask:0x3 d16
|
||||
; GFX81-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX81-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX9-LABEL: image_sample_c_d_1d_v2f16:
|
||||
; GFX9: ; %bb.0: ; %main_body
|
||||
; GFX9-NEXT: image_sample_c_d v0, v[0:3], s[0:7], s[8:11] dmask:0x3 d16
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: image_sample_c_d_1d_v2f16:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_d v0, v[0:3], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D d16
|
||||
; GFX10-NEXT: ; implicit-def: $vcc_hi
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%tex = call <2 x half> @llvm.amdgcn.image.sample.c.d.1d.v2f16.f32.f32(i32 3, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
|
||||
%r = bitcast <2 x half> %tex to float
|
||||
ret float %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_sample_c_d_1d_v2f16_tfe:
|
||||
; GCN: v_mov_b32_e32 v{{[0-9]+}}, 0
|
||||
; UNPACKED: image_sample_c_d v[{{[0-9]+:[0-9]+}}], v[0:3], s[0:7], s[8:11] dmask:0x3 tfe d16{{$}}
|
||||
; PACKED: image_sample_c_d v[{{[0-9]+:[0-9]+}}], v[0:3], s[0:7], s[8:11] dmask:0x3 tfe d16{{$}}
|
||||
define amdgpu_ps <2 x float> @image_sample_c_d_1d_v2f16_tfe(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, float %s) {
|
||||
; TONGA-LABEL: image_sample_c_d_1d_v2f16_tfe:
|
||||
; TONGA: ; %bb.0: ; %main_body
|
||||
; TONGA-NEXT: v_mov_b32_e32 v4, 0
|
||||
; TONGA-NEXT: v_mov_b32_e32 v5, v4
|
||||
; TONGA-NEXT: v_mov_b32_e32 v6, v4
|
||||
; TONGA-NEXT: image_sample_c_d v[4:6], v[0:3], s[0:7], s[8:11] dmask:0x3 tfe d16
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(0)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v0, 16, v5
|
||||
; TONGA-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; TONGA-NEXT: v_mov_b32_e32 v1, v6
|
||||
; TONGA-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX81-LABEL: image_sample_c_d_1d_v2f16_tfe:
|
||||
; GFX81: ; %bb.0: ; %main_body
|
||||
; GFX81-NEXT: v_mov_b32_e32 v4, 0
|
||||
; GFX81-NEXT: v_mov_b32_e32 v5, v4
|
||||
; GFX81-NEXT: s_nop 0
|
||||
; GFX81-NEXT: s_nop 0
|
||||
; GFX81-NEXT: image_sample_c_d v[4:5], v[0:3], s[0:7], s[8:11] dmask:0x3 tfe d16
|
||||
; GFX81-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX81-NEXT: v_mov_b32_e32 v0, v4
|
||||
; GFX81-NEXT: v_mov_b32_e32 v1, v5
|
||||
; GFX81-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX9-LABEL: image_sample_c_d_1d_v2f16_tfe:
|
||||
; GFX9: ; %bb.0: ; %main_body
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, 0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v5, v4
|
||||
; GFX9-NEXT: image_sample_c_d v[4:5], v[0:3], s[0:7], s[8:11] dmask:0x3 tfe d16
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, v4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, v5
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: image_sample_c_d_1d_v2f16_tfe:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: v_mov_b32_e32 v5, v0
|
||||
; GFX10-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX10-NEXT: v_mov_b32_e32 v4, v1
|
||||
; GFX10-NEXT: ; implicit-def: $vcc_hi
|
||||
; GFX10-NEXT: v_mov_b32_e32 v1, v0
|
||||
; GFX10-NEXT: image_sample_c_d v[0:1], [v5, v4, v2, v3], s[0:7], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe d16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%tex = call {<2 x half>,i32} @llvm.amdgcn.image.sample.c.d.1d.v2f16i32.f32.f32(i32 3, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)
|
||||
%tex.vec = extractvalue {<2 x half>, i32} %tex, 0
|
||||
|
|
@ -52,22 +212,120 @@ main_body:
|
|||
ret <2 x float> %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_sample_b_2d_v4f16:
|
||||
; UNPACKED: image_sample_b v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf d16{{$}}
|
||||
; PACKED: image_sample_b v[0:1], v[0:3], s[0:7], s[8:11] dmask:0xf d16{{$}}
|
||||
; GFX10: image_sample_b v[0:1], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D d16{{$}}
|
||||
define amdgpu_ps <2 x float> @image_sample_b_2d_v4f16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t) {
|
||||
; TONGA-LABEL: image_sample_b_2d_v4f16:
|
||||
; TONGA: ; %bb.0: ; %main_body
|
||||
; TONGA-NEXT: s_mov_b64 s[12:13], exec
|
||||
; TONGA-NEXT: s_wqm_b64 exec, exec
|
||||
; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; TONGA-NEXT: image_sample_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf d16
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(0)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
||||
; TONGA-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; TONGA-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; TONGA-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX81-LABEL: image_sample_b_2d_v4f16:
|
||||
; GFX81: ; %bb.0: ; %main_body
|
||||
; GFX81-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GFX81-NEXT: s_wqm_b64 exec, exec
|
||||
; GFX81-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GFX81-NEXT: s_nop 0
|
||||
; GFX81-NEXT: image_sample_b v[0:1], v[0:2], s[0:7], s[8:11] dmask:0xf d16
|
||||
; GFX81-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX81-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX9-LABEL: image_sample_b_2d_v4f16:
|
||||
; GFX9: ; %bb.0: ; %main_body
|
||||
; GFX9-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GFX9-NEXT: s_wqm_b64 exec, exec
|
||||
; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GFX9-NEXT: image_sample_b v[0:1], v[0:2], s[0:7], s[8:11] dmask:0xf d16
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: image_sample_b_2d_v4f16:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: s_mov_b32 s12, exec_lo
|
||||
; GFX10-NEXT: ; implicit-def: $vcc_hi
|
||||
; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
|
||||
; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
||||
; GFX10-NEXT: image_sample_b v[0:1], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D d16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%tex = call <4 x half> @llvm.amdgcn.image.sample.b.2d.v4f16.f32.f32(i32 15, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
|
||||
%r = bitcast <4 x half> %tex to <2 x float>
|
||||
ret <2 x float> %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_sample_b_2d_v4f16_tfe:
|
||||
; GCN: v_mov_b32_e32 v{{[0-9]+}}, 0
|
||||
; UNPACKED: image_sample_b v[{{[0-9]+:[0-9]+}}], v[0:3], s[0:7], s[8:11] dmask:0xf tfe d16{{$}}
|
||||
; PACKED: image_sample_b v[{{[0-9]+:[0-9]+}}], v[0:3], s[0:7], s[8:11] dmask:0xf tfe d16{{$}}
|
||||
define amdgpu_ps <4 x float> @image_sample_b_2d_v4f16_tfe(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t) {
|
||||
; TONGA-LABEL: image_sample_b_2d_v4f16_tfe:
|
||||
; TONGA: ; %bb.0: ; %main_body
|
||||
; TONGA-NEXT: s_mov_b64 s[12:13], exec
|
||||
; TONGA-NEXT: s_wqm_b64 exec, exec
|
||||
; TONGA-NEXT: v_mov_b32_e32 v3, 0
|
||||
; TONGA-NEXT: v_mov_b32_e32 v4, v3
|
||||
; TONGA-NEXT: v_mov_b32_e32 v5, v3
|
||||
; TONGA-NEXT: v_mov_b32_e32 v6, v3
|
||||
; TONGA-NEXT: v_mov_b32_e32 v7, v3
|
||||
; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; TONGA-NEXT: image_sample_b v[3:7], v[0:2], s[0:7], s[8:11] dmask:0xf tfe d16
|
||||
; TONGA-NEXT: s_waitcnt vmcnt(0)
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v0, 16, v4
|
||||
; TONGA-NEXT: v_lshlrev_b32_e32 v1, 16, v6
|
||||
; TONGA-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; TONGA-NEXT: v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; TONGA-NEXT: v_mov_b32_e32 v2, v7
|
||||
; TONGA-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX81-LABEL: image_sample_b_2d_v4f16_tfe:
|
||||
; GFX81: ; %bb.0: ; %main_body
|
||||
; GFX81-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GFX81-NEXT: s_wqm_b64 exec, exec
|
||||
; GFX81-NEXT: v_mov_b32_e32 v3, 0
|
||||
; GFX81-NEXT: v_mov_b32_e32 v4, v3
|
||||
; GFX81-NEXT: v_mov_b32_e32 v5, v3
|
||||
; GFX81-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GFX81-NEXT: s_nop 0
|
||||
; GFX81-NEXT: image_sample_b v[3:5], v[0:2], s[0:7], s[8:11] dmask:0xf tfe d16
|
||||
; GFX81-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX81-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX81-NEXT: v_mov_b32_e32 v1, v4
|
||||
; GFX81-NEXT: v_mov_b32_e32 v2, v5
|
||||
; GFX81-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX9-LABEL: image_sample_b_2d_v4f16_tfe:
|
||||
; GFX9: ; %bb.0: ; %main_body
|
||||
; GFX9-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GFX9-NEXT: s_wqm_b64 exec, exec
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, 0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v4, v3
|
||||
; GFX9-NEXT: v_mov_b32_e32 v5, v3
|
||||
; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GFX9-NEXT: image_sample_b v[3:5], v[0:2], s[0:7], s[8:11] dmask:0xf tfe d16
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, v3
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, v4
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, v5
|
||||
; GFX9-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: image_sample_b_2d_v4f16_tfe:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: s_mov_b32 s12, exec_lo
|
||||
; GFX10-NEXT: ; implicit-def: $vcc_hi
|
||||
; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
|
||||
; GFX10-NEXT: v_mov_b32_e32 v3, v0
|
||||
; GFX10-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX10-NEXT: v_mov_b32_e32 v5, v2
|
||||
; GFX10-NEXT: v_mov_b32_e32 v4, v1
|
||||
; GFX10-NEXT: v_mov_b32_e32 v1, v0
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
||||
; GFX10-NEXT: image_sample_b v[0:2], v[3:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D tfe d16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
%tex = call {<4 x half>,i32} @llvm.amdgcn.image.sample.b.2d.v4f16i32.f32.f32(i32 15, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)
|
||||
%tex.vec = extractvalue {<4 x half>, i32} %tex, 0
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -27,7 +27,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_l_2d:
|
||||
; GCN: image_sample_c_lz v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_lz v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -43,7 +43,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_l_o_2d:
|
||||
; GCN: image_sample_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -51,7 +51,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_l_o_1d:
|
||||
; GCN: image_sample_c_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %lod) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -75,7 +75,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}gather4_c_l_2d:
|
||||
; GCN: image_gather4_c_lz v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_gather4_c_lz v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -83,7 +83,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}gather4_l_o_2d:
|
||||
; GCN: image_gather4_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_gather4_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @gather4_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_o_2d:
|
||||
; GCN: image_sample_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -18,7 +18,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_o_1d:
|
||||
; GCN: image_sample_c_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -34,7 +34,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cl_o_1d:
|
||||
; GCN: image_sample_cl_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_cl_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cl_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %clamp) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cl.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -66,7 +66,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_b_o_1d:
|
||||
; GCN: image_sample_b_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_b_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_b_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %s) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %bias, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -258,7 +258,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_l_o_1d:
|
||||
; GCN: image_sample_l_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_l_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %lod) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -298,7 +298,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_lz_o_2d:
|
||||
; GCN: image_sample_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_lz_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.lz.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -306,7 +306,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_lz_o_1d:
|
||||
; GCN: image_sample_c_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_lz_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue