diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 55b06aabbffd..d5c176a7e216 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -93,9 +93,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
 
   setAction({G_BRCOND, S1}, Legal);
 
-  setAction({G_ASHR, S32}, Legal);
-  setAction({G_ASHR, 1, S32}, Legal);
-
   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_UMULH, G_SMULH})
     .legalFor({S32})
     .scalarize(0);
@@ -186,6 +183,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
     setAction({G_GEP, 1, IdxTy}, Legal);
   }
 
+  // FIXME: When RegBankSelect inserts copies, it will only create new registers
+  // with scalar types. This means we can end up with G_LOAD/G_STORE/G_GEP
+  // instruction with scalar types for their pointer operands. In assert builds,
+  // the instruction selector will assert if it sees a generic instruction which
+  // isn't legal, so we need to tell it that scalar types are legal for pointer
+  // operands
+  setAction({G_GEP, S64}, Legal);
+
   setAction({G_BLOCK_ADDR, CodePtr}, Legal);
 
   getActionDefinitionsBuilder({G_ICMP, G_FCMP})
@@ -288,14 +293,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
     Shifts.clampScalar(0, S32, S64);
   Shifts.clampScalar(1, S32, S32);
 
-  // FIXME: When RegBankSelect inserts copies, it will only create new
-  // registers with scalar types.  This means we can end up with
-  // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
-  // operands.  In assert builds, the instruction selector will assert
-  // if it sees a generic instruction which isn't legal, so we need to
-  // tell it that scalar types are legal for pointer operands
-  setAction({G_GEP, S64}, Legal);
-
   for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
     unsigned VecTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 1 : 0;
     unsigned EltTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 0 : 1;