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Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP. 

llvm-svn: 185926
This commit is contained in:
Joey Gouly 2013-07-09 11:03:21 +00:00
parent d7f6a6196e
commit 3b693c42b5
3 changed files with 55 additions and 0 deletions
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21
llvm/lib/Target/ARM/ARMInstrVFP.td
View File

@ -648,6 +648,27 @@ def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
} }
multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
[]>, Requires<[HasV8FP]> {
let Inst{7} = op2;
let Inst{16} = op;
}
def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
(outs DPR:$Dd), (ins DPR:$Dm),
NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
[]>, Requires<[HasV8FP]> {
let Inst{7} = op2;
let Inst{16} = op;
}
}
defm VRINTZ : vrint_inst_zrx<"z", 0, 1>;
defm VRINTR : vrint_inst_zrx<"r", 0, 0>;
defm VRINTX : vrint_inst_zrx<"x", 1, 0>;
def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
(outs DPR:$Dd), (ins DPR:$Dm), (outs DPR:$Dd), (ins DPR:$Dm),
IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",

15
llvm/test/MC/ARM/v8fp.s
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@ -88,3 +88,18 @@
@ CHECK: vminnm.f32 s0, s0, s12 @ encoding: [0x46,0x0a,0x80,0xfe] @ CHECK: vminnm.f32 s0, s0, s12 @ encoding: [0x46,0x0a,0x80,0xfe]
vminnm.f64 d4, d6, d9 vminnm.f64 d4, d6, d9
@ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x49,0x4b,0x86,0xfe] @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x49,0x4b,0x86,0xfe]
@ VRINT{Z,R,X}
vrintzge.f64 d3, d12
@ CHECK: vrintzge.f64 d3, d12 @ encoding: [0xcc,0x3b,0xb6,0xae]
vrintz.f32 s3, s24
@ CHECK: vrintz.f32 s3, s24 @ encoding: [0xcc,0x1a,0xf6,0xee]
vrintrlt.f64 d5, d0
@ CHECK: vrintrlt.f64 d5, d0 @ encoding: [0x40,0x5b,0xb6,0xbe]
vrintr.f32 s0, s9
@ CHECK: vrintr.f32 s0, s9 @ encoding: [0x64,0x0a,0xb6,0xee]
vrintxeq.f64 d28, d30
@ CHECK: vrintxeq.f64 d28, d30 @ encoding: [0x6e,0xcb,0xf7,0x0e]
vrintxvs.f32 s10, s14
@ CHECK: vrintxvs.f32 s10, s14 @ encoding: [0x47,0x5a,0xb7,0x6e]

19
llvm/test/MC/Disassembler/ARM/v8fp.txt
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@ -110,3 +110,22 @@
0x49 0x4b 0x86 0xfe 0x49 0x4b 0x86 0xfe
# CHECK: vminnm.f64 d4, d6, d9 # CHECK: vminnm.f64 d4, d6, d9
0xcc 0x3b 0xb6 0xae
# CHECK: vrintzge.f64 d3, d12
0xcc 0x1a 0xf6 0xee
# CHECK: vrintz.f32 s3, s24
0x40 0x5b 0xb6 0xbe
# CHECK: vrintrlt.f64 d5, d0
0x64 0x0a 0xb6 0xee
# CHECK: vrintr.f32 s0, s9
0x6e 0xcb 0xf7 0x0e
# CHECK: vrintxeq.f64 d28, d30
0x47 0x5a 0xb7 0x6e
# CHECK: vrintxvs.f32 s10, s14