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Add initial support for immediates. This allows us to compile this: 

int %rlwnm(int %A, int %B) {
  %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
  ret int %C
}

into:

_rlwnm:
        or r2, r3, r3
        or r3, r4, r4
        rlwnm r2, r2, r3, 4, 17    ;; note the immediates :)
        or r3, r2, r2
        blr

llvm-svn: 25955
This commit is contained in:
Chris Lattner 2006-02-04 02:26:14 +00:00
parent 0a977c95aa
commit 3b48431333
2 changed files with 16 additions and 6 deletions
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20
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -300,16 +300,26 @@ void ScheduleDAG::EmitNode(NodeInfo *NI) {
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps; i += 2) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
unsigned Flags =cast<ConstantSDNode>(Node->getOperand(i+1))->getValue();
MachineOperand::UseType UseTy;
switch (Flags) {
default: assert(0 && "Bad flags!");
case 1: UseTy = MachineOperand::Use; break;
case 2: UseTy = MachineOperand::Def; break;
case 3: UseTy = MachineOperand::UseAndDef; break;
case 1: { // Use of register.
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addMachineRegOperand(Reg, MachineOperand::Use);
break;
}
case 2: { // Def of register.
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addMachineRegOperand(Reg, MachineOperand::Def);
break;
}
case 3: { // Immediate.
uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
MI->addZeroExtImm64Operand(Val);
break;
}
}
MI->addMachineRegOperand(Reg, UseTy);
}
break;
}

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1366,7 +1366,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
// Add information to the INLINEASM node to know about this input.
AsmNodeOperands.push_back(ResOp);
AsmNodeOperands.push_back(DAG.getConstant(1, MVT::i32)); // ISUSE
AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
break;
}
case InlineAsm::isClobber: