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[X86][CLMUL] Use the default CLMUL scheduler classes directly. NFCI. 

Models were completely overriding all CLMUL instructions when the WriteCLMUL default classes could be used for exactly the same coverage.

llvm-svn: 328194
This commit is contained in:
Simon Pilgrim 2018-03-22 13:37:30 +00:00
parent 6bdd6b32fd
commit 3b2ff1faa9
4 changed files with 23 additions and 63 deletions
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6
llvm/lib/Target/X86/X86SchedBroadwell.td
View File

@ -243,7 +243,7 @@ def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
}
// Carry-less multiplication instructions.
defm : BWWriteResPair<WriteCLMul, [BWPort0, BWPort5], 7, [2, 1]>;
defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
// Catch-all for expensive system instructions.
def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
@ -1518,7 +1518,6 @@ def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
"MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
"PCLMULQDQrr",
"PCMPGTQrr",
"PHMINPOSUWrr",
"PMADDUBSWrr",
@ -1534,7 +1533,6 @@ def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
"RCPSSr",
"RSQRTPSr",
"RSQRTSSr",
"VPCLMULQDQrr",
"VPCMPGTQYrr",
"VPCMPGTQrr",
"VPHMINPOSUWrr",
@ -2812,7 +2810,6 @@ def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
"MMX_PMULLWirm",
"MMX_PMULUDQirm",
"MMX_PSADBWirm",
"PCLMULQDQrm",
"PCMPGTQrm",
"PHMINPOSUWrm",
"PMADDUBSWrm",
@ -2828,7 +2825,6 @@ def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
"RCPSSm",
"RSQRTPSm",
"RSQRTSSm",
"VPCLMULQDQrm",
"VPCMPGTQrm",
"VPHMINPOSUWrm",
"VPMADDUBSWrm",

24
llvm/lib/Target/X86/X86SchedHaswell.td
View File

@ -243,12 +243,14 @@ def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> {
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
let Latency = 7;
let ResourceCycles = [2, 1];
let Latency = 11;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
let Latency = 7;
let ResourceCycles = [2, 1, 1];
let Latency = 17;
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
@ -2947,13 +2949,6 @@ def HWWriteResGroup123 : SchedWriteRes<[HWPort0]> {
def: InstRW<[HWWriteResGroup123], (instregex "(V?)PCMPISTRIrr",
"(V?)PCMPISTRM128rr")>;
def HWWriteResGroup124 : SchedWriteRes<[HWPort0,HWPort5]> {
let Latency = 11;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
def: InstRW<[HWWriteResGroup124], (instregex "(V?)PCLMULQDQrr")>;
def HWWriteResGroup125 : SchedWriteRes<[HWPort0,HWPort015]> {
let Latency = 11;
let NumMicroOps = 3;
@ -2970,13 +2965,6 @@ def HWWriteResGroup126 : SchedWriteRes<[HWPort0,HWPort23]> {
def: InstRW<[HWWriteResGroup126], (instregex "(V?)PCMPISTRIrm",
"(V?)PCMPISTRM128rm")>;
def HWWriteResGroup127 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
let Latency = 17;
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
def: InstRW<[HWWriteResGroup127], (instregex "(V?)PCLMULQDQrm")>;
def HWWriteResGroup128 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> {
let Latency = 18;
let NumMicroOps = 4;

28
llvm/lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -246,13 +246,15 @@ def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
}
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [SKLPort0, SKLPort5]> {
let Latency = 7;
let ResourceCycles = [2, 1];
def : WriteRes<WriteCLMul, [SKLPort5]> {
let Latency = 6;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def : WriteRes<WriteCLMulLd, [SKLPort0, SKLPort5, SKLPort23]> {
let Latency = 7;
let ResourceCycles = [2, 1, 1];
def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
let Latency = 12;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
// Catch-all for expensive system instructions.
@ -1703,13 +1705,6 @@ def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF16",
"PUSHF64")>;
def SKLWriteResGroup66 : SchedWriteRes<[SKLPort5]> {
let Latency = 6;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup66], (instregex "(V?)PCLMULQDQrr")>;
def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
let Latency = 6;
let NumMicroOps = 1;
@ -3140,13 +3135,6 @@ def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPSYr",
"VSQRTPSr",
"VSQRTSSr")>;
def SKLWriteResGroup158 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 12;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup158], (instregex "(V?)PCLMULQDQrm")>;
def SKLWriteResGroup159 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
let Latency = 12;
let NumMicroOps = 4;

28
llvm/lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -246,13 +246,15 @@ def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
}
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [SKXPort0, SKXPort5]> {
let Latency = 7;
let ResourceCycles = [2, 1];
def : WriteRes<WriteCLMul, [SKXPort5]> {
let Latency = 6;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def : WriteRes<WriteCLMulLd, [SKXPort0, SKXPort5, SKXPort23]> {
let Latency = 7;
let ResourceCycles = [2, 1, 1];
def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
let Latency = 12;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
// Catch-all for expensive system instructions.
@ -2856,13 +2858,6 @@ def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF16",
"PUSHF64")>;
def SKXWriteResGroup70 : SchedWriteRes<[SKXPort5]> {
let Latency = 6;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup70], (instregex "(V?)PCLMULQDQrr")>;
def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
let Latency = 6;
let NumMicroOps = 1;
@ -5378,13 +5373,6 @@ def: InstRW<[SKXWriteResGroup172], (instregex "SQRTPSr",
"VSQRTSSZr(b?)(_Int)?(k?)(z?)",
"VSQRTSSr")>;
def SKXWriteResGroup173 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 12;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup173], (instregex "(V?)PCLMULQDQrm")>;
def SKXWriteResGroup174 : SchedWriteRes<[SKXPort015]> {
let Latency = 12;
let NumMicroOps = 3;