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When the scheduler unfold a load folding instruction it move some of the predecessors to the unfolded load. It decides what gets moved to the load by checking whether the new load is using the predecessor as an operand. The check neglects the cases whether the predecessor is a flagged scheduling unit. 

rdar://7604000

llvm-svn: 95339
This commit is contained in:
Evan Cheng 2010-02-05 01:27:11 +00:00
parent 6510dc8dc3
commit 3b245876c0
2 changed files with 38 additions and 2 deletions
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12
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -345,6 +345,15 @@ void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle,
++NumBacktracks;
}
static bool isOperandOf(const SUnit *SU, SDNode *N) {
for (const SDNode *SUNode = SU->getNode(); SUNode;
SUNode = SUNode->getFlaggedNode()) {
if (SUNode->isOperandOf(N))
return true;
}
return false;
}
/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
/// successors to the newly created node.
SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
@ -427,8 +436,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
I != E; ++I) {
if (I->isCtrl())
ChainPreds.push_back(*I);
else if (I->getSUnit()->getNode() &&
I->getSUnit()->getNode()->isOperandOf(LoadNode))
else if (isOperandOf(I->getSUnit(), LoadNode))
LoadPreds.push_back(*I);
else
NodePreds.push_back(*I);

28
llvm/test/CodeGen/X86/2010-02-04-SchedulerBug.ll Normal file
View File

@ -0,0 +1,28 @@
; RUN: llc < %s -mtriple=i386-apple-darwin11
; rdar://7604000
%struct.a_t = type { i8*, i64*, i8*, i32, i32, i64*, i64*, i64* }
%struct.b_t = type { i32, i32, i32, i32, i64, i64, i64, i64 }
define void @t(i32 %cNum, i64 %max) nounwind optsize ssp noimplicitfloat {
entry:
%0 = load %struct.b_t** null, align 4 ; <%struct.b_t*> [#uses=1]
%1 = getelementptr inbounds %struct.b_t* %0, i32 %cNum, i32 5 ; <i64*> [#uses=1]
%2 = load i64* %1, align 4 ; <i64> [#uses=1]
%3 = icmp ult i64 %2, %max ; <i1> [#uses=1]
%4 = getelementptr inbounds %struct.a_t* null, i32 0, i32 7 ; <i64**> [#uses=1]
%5 = load i64** %4, align 4 ; <i64*> [#uses=0]
%6 = load i64* null, align 4 ; <i64> [#uses=1]
br i1 %3, label %bb2, label %bb
bb: ; preds = %entry
br label %bb3
bb2: ; preds = %entry
%7 = or i64 %6, undef ; <i64> [#uses=1]
br label %bb3
bb3: ; preds = %bb2, %bb
%misc_enables.0 = phi i64 [ undef, %bb ], [ %7, %bb2 ] ; <i64> [#uses=0]
ret void
}