From 3b21823e4abb501ca0b0de7777493be56a11cb67 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 25 Jul 2020 12:08:06 +0100 Subject: [PATCH] [X86][SSE] combineX86ShufflesRecursively - move all Root node asserts to the same location. NFCI. Minor tidyup for some upcoming shuffle combine improvements. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4dc68d469bba..24bc264df129 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -35346,6 +35346,9 @@ static SDValue combineX86ShufflesRecursively( assert(RootMask.size() > 0 && (RootMask.size() > 1 || (RootMask[0] == 0 && SrcOpIndex == 0)) && "Illegal shuffle root mask"); + assert(Root.getSimpleValueType().isVector() && + "Shuffles operate on vector types!"); + unsigned RootSizeInBits = Root.getSimpleValueType().getSizeInBits(); // Bound the depth of our recursive combine because this is ultimately // quadratic in nature. @@ -35361,9 +35364,6 @@ static SDValue combineX86ShufflesRecursively( if (!VT.isVector()) return SDValue(); // Bail if we hit a non-vector. - assert(Root.getSimpleValueType().isVector() && - "Shuffles operate on vector types!"); - unsigned RootSizeInBits = Root.getSimpleValueType().getSizeInBits(); assert(VT.getSizeInBits() == RootSizeInBits && "Can only combine shuffles of the same vector register size.");