forked from OSchip/llvm-project
Remove unused ARMISD::AND selection DAG node.
llvm-svn: 116566
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@ -737,7 +737,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
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case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
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case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
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case ARMISD::AND: return "ARMISD::AND";
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case ARMISD::CMP: return "ARMISD::CMP";
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case ARMISD::CMPZ: return "ARMISD::CMPZ";
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case ARMISD::CMPFP: return "ARMISD::CMPFP";
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@ -47,8 +47,6 @@ namespace llvm {
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PIC_ADD, // Add with a PC operand and a PIC label.
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AND, // ARM "and" instruction that sets the 's' flag in CPSR.
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CMP, // ARM compare instructions.
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CMPZ, // ARM compare that sets only Z flag.
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CMPFP, // ARM VFP compare instruction, sets FPSCR.
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@ -106,9 +106,6 @@ def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
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def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
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[SDNPHasChain]>;
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def ARMand : SDNode<"ARMISD::AND", SDT_ARMAnd,
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[SDNPOutFlag]>;
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def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
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[SDNPOutFlag]>;
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@ -2028,9 +2025,6 @@ def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
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defm AND : AsI1_bin_irs<0b0000, "and",
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IIC_iBITi, IIC_iBITr, IIC_iBITsr,
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BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
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defm ANDS : AI1_bin_s_irs<0b0000, "and",
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IIC_iBITi, IIC_iBITr, IIC_iBITsr,
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BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>;
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defm ORR : AsI1_bin_irs<0b1100, "orr",
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IIC_iBITi, IIC_iBITr, IIC_iBITsr,
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BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
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@ -1658,10 +1658,6 @@ defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
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IIC_iBITi, IIC_iBITr, IIC_iBITsi,
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BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
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defm t2ANDS : T2I_bin_s_irs<0b0000, "and",
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IIC_iBITi, IIC_iBITr, IIC_iBITsi,
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BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>;
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let Constraints = "$src = $dst" in
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def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
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IIC_iUNAsi, "bfc", "\t$dst, $imm",
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