forked from OSchip/llvm-project
[X86][AVX] Improve (i4 bitcast (v4i1 x)) handling for 256-bit vector compare results.
As commented on D37849 and rL313547, AVX1 targets were missing a chance to use vmovmskpd for v4f64/v4i64 results for bool vector bitcasts llvm-svn: 314293
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@ -29321,7 +29321,7 @@ static SDValue combineBitcastvxi1(SelectionDAG &DAG, SDValue BitCast,
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// sign-extend to a 256-bit operation to avoid truncation.
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if (N0->getOpcode() == ISD::SETCC &&
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N0->getOperand(0)->getValueType(0).is256BitVector() &&
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Subtarget.hasInt256()) {
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Subtarget.hasAVX()) {
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SExtVT = MVT::v4i64;
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FPCastVT = MVT::v4f64;
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}
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@ -222,8 +222,8 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vmovmskps %xmm0, %eax
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vmovmskpd %ymm0, %eax
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; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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@ -259,23 +259,13 @@ define i4 @v4f64(<4 x double> %a, <4 x double> %b) {
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; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; SSE2-SSSE3-NEXT: retq
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;
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; AVX1-LABEL: v4f64:
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; AVX1: # BB#0:
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; AVX1-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vmovmskps %xmm0, %eax
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; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: v4f64:
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; AVX2: # BB#0:
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; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: vmovmskpd %ymm0, %eax
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; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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; AVX12-LABEL: v4f64:
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; AVX12: # BB#0:
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; AVX12-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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; AVX12-NEXT: vmovmskpd %ymm0, %eax
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; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; AVX12-NEXT: vzeroupper
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; AVX12-NEXT: retq
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;
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; AVX512-LABEL: v4f64:
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; AVX512: # BB#0:
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