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GlobalISel: Handle more cases in lowerUnmergeValues 

Handle scalar sources, as well as vectors.
This commit is contained in:
Matt Arsenault 2020-03-29 18:04:53 -04:00 committed by Matt Arsenault
parent 24b3c2d058
commit 3af85fa8f0
11 changed files with 1531 additions and 1691 deletions
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7
llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
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@ -98,6 +98,13 @@ public:
/// Expose LegalizerInfo so the clients can re-use.
const LegalizerInfo &getLegalizerInfo() const { return LI; }
/// Cast the given value to an LLT::scalar with an equivalent size. Returns
/// the register to use if an instruction was inserted. Returns the original
/// register if no coercion was necessary.
//
// This may also fail and return Register() if there is no legal way to cast.
Register coerceToScalar(Register Val);
/// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
/// Use by extending the operand's type to \p WideTy using the specified \p
/// ExtOpcode for the extension instruction, and replacing the vreg of the

57
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -1213,6 +1213,28 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
}
}
Register LegalizerHelper::coerceToScalar(Register Val) {
LLT Ty = MRI.getType(Val);
if (Ty.isScalar())
return Val;
const DataLayout &DL = MIRBuilder.getDataLayout();
LLT NewTy = LLT::scalar(Ty.getSizeInBits());
if (Ty.isPointer()) {
if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace()))
return Register();
return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0);
}
Register NewVal = Val;
assert(Ty.isVector());
LLT EltTy = Ty.getElementType();
if (EltTy.isPointer())
NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0);
return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0);
}
void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
unsigned OpIdx, unsigned ExtOpcode) {
MachineOperand &MO = MI.getOperand(OpIdx);
@ -4906,34 +4928,31 @@ LegalizerHelper::lowerMergeValues(MachineInstr &MI) {
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
const unsigned NumDst = MI.getNumOperands() - 1;
const Register SrcReg = MI.getOperand(NumDst).getReg();
LLT SrcTy = MRI.getType(SrcReg);
Register SrcReg = MI.getOperand(NumDst).getReg();
Register Dst0Reg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(Dst0Reg);
if (DstTy.isPointer())
return UnableToLegalize; // TODO
SrcReg = coerceToScalar(SrcReg);
if (!SrcReg)
return UnableToLegalize;
// Expand scalarizing unmerge as bitcast to integer and shift.
if (!DstTy.isVector() && SrcTy.isVector() &&
SrcTy.getElementType() == DstTy) {
LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
LLT IntTy = MRI.getType(SrcReg);
MIRBuilder.buildTrunc(Dst0Reg, Cast);
MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
const unsigned DstSize = DstTy.getSizeInBits();
unsigned Offset = DstSize;
for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
}
MI.eraseFromParent();
return Legalized;
const unsigned DstSize = DstTy.getSizeInBits();
unsigned Offset = DstSize;
for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt);
MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
}
return UnableToLegalize;
MI.eraseFromParent();
return Legalized;
}
LegalizerHelper::LegalizeResult

12
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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@ -1229,17 +1229,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
};
auto &Builder = getActionDefinitionsBuilder(Op)
.lowerFor({{S16, V2S16}});
// FIXME: Hack until unmerge handled
if (Op == G_MERGE_VALUES) {
Builder.lowerIf([=](const LegalityQuery &Query) {
.lowerFor({{S16, V2S16}})
.lowerIf([=](const LegalityQuery &Query) {
const LLT BigTy = Query.Types[BigTyIdx];
return BigTy.getSizeInBits() == 32;
});
}
Builder
})
// Try to widen to s16 first for small types.
// TODO: Only do this on targets with legal s16 shifts
.minScalarOrEltIf(narrowerThan(LitTyIdx, 16), LitTyIdx, S16)

23
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
View File

@ -409,9 +409,26 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY1]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<2 x s16>)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<2 x s16>)
; CHECK: S_ENDPGM 0, implicit [[UV]](s8), implicit [[UV1]](s8), implicit [[UV2]](s8), implicit [[UV3]](s8), implicit [[UV4]](s8), implicit [[UV5]](s8), implicit [[UV6]](s8), implicit [[UV7]](s8)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<2 x s16>)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[BITCAST]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[LSHR1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[LSHR2]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC1]](<2 x s16>)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[BITCAST1]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[LSHR3]](s32)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[LSHR4]](s32)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s8) = G_TRUNC [[LSHR5]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC2]](s8), implicit [[TRUNC3]](s8), implicit [[TRUNC4]](s8), implicit [[TRUNC5]](s8), implicit [[TRUNC6]](s8), implicit [[TRUNC7]](s8), implicit [[TRUNC8]](s8), implicit [[TRUNC9]](s8)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<4 x s32>) = G_CONCAT_VECTORS %0, %1

21
llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
View File

@ -229,13 +229,10 @@ define <4 x float> @v_uitofp_v4i8_to_v4f32(i32 %arg0) nounwind {
; SI-LABEL: v_uitofp_v4i8_to_v4f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, 0xffff
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT: v_and_b32_e32 v1, s4, v0
; SI-NEXT: v_and_b32_e32 v3, s4, v2
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; SI-NEXT: s_movk_i32 s4, 0xff
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; SI-NEXT: v_and_b32_e32 v0, s4, v0
; SI-NEXT: v_and_b32_e32 v1, s4, v1
; SI-NEXT: v_and_b32_e32 v2, s4, v2
@ -250,14 +247,14 @@ define <4 x float> @v_uitofp_v4i8_to_v4f32(i32 %arg0) nounwind {
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_movk_i32 s4, 0xff
; VI-NEXT: v_mov_b32_e32 v5, s4
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; VI-NEXT: v_and_b32_sdwa v2, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_and_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v0
; VI-NEXT: v_and_b32_sdwa v0, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_and_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; VI-NEXT: v_cvt_f32_ubyte0_e32 v3, v0
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
; VI-NEXT: v_mov_b32_e32 v0, v4
; VI-NEXT: s_setpc_b64 s[30:31]
%val = bitcast i32 %arg0 to <4 x i8>

52
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
View File

@ -564,45 +564,45 @@ body: |
; CHECK-LABEL: name: test_anyext_s32_to_s88
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C2]]
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C1]](s16)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C4]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[OR2]](s16)
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[OR2]](s16)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[COPY5]](s16)
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[COPY1]](s16)
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C1]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR3]](s32), [[OR4]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV1:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC3]](s88)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC5]](s88)
%0:_(s32) = COPY $vgpr0
%1:_(s88) = G_ANYEXT %0
S_ENDPGM 0, implicit %1

48
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
View File

@ -779,21 +779,45 @@ body: |
name: test_freeze_v4s8
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-LABEL: name: test_freeze_v4s8
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s8>) = COPY $vgpr0
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<4 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(<4 x s32>) = G_FREEZE [[BUILD_VECTOR]]
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[FREEZE]](<4 x s32>)
; CHECK: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
%0:_(<4 x s8>) = COPY $vgpr0
%1:_(<4 x s8>) = G_FREEZE %0
$vgpr0 = COPY %1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FREEZE]](<4 x s32>)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; CHECK: S_ENDPGM 0, implicit [[COPY12]](s32), implicit [[COPY13]](s32), implicit [[COPY14]](s32), implicit [[COPY15]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
%3:_(s32) = COPY $vgpr3
%4:_(s8) = G_TRUNC %0
%5:_(s8) = G_TRUNC %1
%6:_(s8) = G_TRUNC %2
%7:_(s8) = G_TRUNC %3
%8:_(<4 x s8>) = G_BUILD_VECTOR %4, %5, %6, %7
%9:_(<4 x s8>) = G_FREEZE %8
%10:_(s8), %11:_(s8), %12:_(s8), %13:_(s8) = G_UNMERGE_VALUES %9
%14:_(s32) = G_ANYEXT %10
%15:_(s32) = G_ANYEXT %11
%16:_(s32) = G_ANYEXT %12
%17:_(s32) = G_ANYEXT %13
S_ENDPGM 0, implicit %14, implicit %15, implicit %16, implicit %17
...
---

116
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
View File

@ -602,88 +602,88 @@ body: |
; CHECK-LABEL: name: test_sext_s32_to_s88
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[COPY1]], [[C1]](s16)
; CHECK: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 7
; CHECK: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[C2]](s16)
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16)
; CHECK: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C3]](s16)
; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 7
; CHECK: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[C4]](s16)
; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C5]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C5]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C3]]
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C5]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C5]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C3]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C3]]
; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C3]]
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C1]](s16)
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C5]]
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C5]]
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C3]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL3]]
; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C3]]
; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C3]]
; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C1]](s16)
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C5]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C5]]
; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C3]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL4]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL5]]
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C1]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL6]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C3]]
; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C3]]
; CHECK: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C1]](s16)
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C5]]
; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C5]]
; CHECK: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C3]](s16)
; CHECK: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[SHL7]]
; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C3]]
; CHECK: [[COPY13:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND11:%[0-9]+]]:_(s16) = G_AND [[COPY13]], [[C3]]
; CHECK: [[SHL8:%[0-9]+]]:_(s16) = G_SHL [[AND11]], [[C1]](s16)
; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C5]]
; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND11:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C5]]
; CHECK: [[SHL8:%[0-9]+]]:_(s16) = G_SHL [[AND11]], [[C3]](s16)
; CHECK: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[SHL8]]
; CHECK: [[COPY14:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[COPY14]], [[C3]]
; CHECK: [[COPY15:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND13:%[0-9]+]]:_(s16) = G_AND [[COPY15]], [[C3]]
; CHECK: [[SHL9:%[0-9]+]]:_(s16) = G_SHL [[AND13]], [[C1]](s16)
; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C5]]
; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND13:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C5]]
; CHECK: [[SHL9:%[0-9]+]]:_(s16) = G_SHL [[AND13]], [[C3]](s16)
; CHECK: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[SHL9]]
; CHECK: [[COPY16:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND14:%[0-9]+]]:_(s16) = G_AND [[COPY16]], [[C3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[COPY17]], [[C3]]
; CHECK: [[SHL10:%[0-9]+]]:_(s16) = G_SHL [[AND15]], [[C1]](s16)
; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND14:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C5]]
; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C5]]
; CHECK: [[SHL10:%[0-9]+]]:_(s16) = G_SHL [[AND15]], [[C3]](s16)
; CHECK: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[SHL10]]
; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[OR7]](s16)
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C]](s32)
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C1]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL11]]
; CHECK: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[OR8]](s16)
; CHECK: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[OR9]](s16)
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[ZEXT7]], [[C]](s32)
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[ZEXT7]], [[C1]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[SHL12]]
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR10]](s32), [[OR11]](s32)
; CHECK: [[MV2:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s88) = G_TRUNC [[MV2]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC2]](s88)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s88) = G_TRUNC [[MV2]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC5]](s88)
%0:_(s32) = COPY $vgpr0
%1:_(s88) = G_SEXT %0
S_ENDPGM 0, implicit %1

2665
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
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File diff suppressed because it is too large Load Diff

167
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
View File

@ -194,25 +194,20 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: $vgpr1 = COPY [[COPY5]](s32)
; CHECK: $vgpr2 = COPY [[COPY6]](s32)
; CHECK: $vgpr3 = COPY [[COPY7]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr1 = COPY [[COPY2]](s32)
; CHECK: $vgpr2 = COPY [[COPY3]](s32)
; CHECK: $vgpr3 = COPY [[COPY4]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
@ -670,25 +665,20 @@ body: |
; CHECK-LABEL: name: test_unmerge_s8_p3
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: $vgpr1 = COPY [[COPY5]](s32)
; CHECK: $vgpr2 = COPY [[COPY6]](s32)
; CHECK: $vgpr3 = COPY [[COPY7]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr1 = COPY [[COPY2]](s32)
; CHECK: $vgpr2 = COPY [[COPY3]](s32)
; CHECK: $vgpr3 = COPY [[COPY4]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
@ -961,3 +951,108 @@ body: |
S_NOP 0, implicit %1
S_NOP 0, implicit %2
...
name: test_unmerge_s8_v4s8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_v4s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr1 = COPY [[COPY2]](s32)
; CHECK: $vgpr2 = COPY [[COPY3]](s32)
; CHECK: $vgpr3 = COPY [[COPY4]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %1
%6:_(s32) = G_ANYEXT %2
%7:_(s32) = G_ANYEXT %3
%8:_(s32) = G_ANYEXT %4
%9:_(s32) = G_ANYEXT %5
$vgpr0 = COPY %6
$vgpr1 = COPY %7
$vgpr2 = COPY %8
$vgpr3 = COPY %9
...
---
name: test_unmerge_s8_v3s8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_v3s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: $vgpr1 = COPY [[COPY5]](s32)
; CHECK: $vgpr2 = COPY [[COPY6]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(<3 x s8>) = G_BITCAST %1
%3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %2
%6:_(s32) = G_ANYEXT %3
%7:_(s32) = G_ANYEXT %4
%8:_(s32) = G_ANYEXT %5
$vgpr0 = COPY %6
$vgpr1 = COPY %7
$vgpr2 = COPY %8
...
---
name: test_unmerge_s8_v2s8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_v2s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr1 = COPY [[COPY3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(<2 x s8>) = G_BITCAST %1
%3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %2
%5:_(s32) = G_ANYEXT %3
%6:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
$vgpr1 = COPY %6
...

54
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
View File

@ -605,44 +605,44 @@ body: |
; CHECK-LABEL: name: test_zext_s32_to_s88
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C2]]
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C3]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C1]](s16)
; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C4]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[OR2]](s16)
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[OR2]](s16)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[COPY5]](s16)
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[COPY1]](s16)
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C1]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR3]](s32), [[OR4]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV1:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC2]](s88)
; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV1:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC4]](s88)
%0:_(s32) = COPY $vgpr0
%1:_(s88) = G_ZEXT %0
S_ENDPGM 0, implicit %1