forked from OSchip/llvm-project
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4efa77fde4
commit
3aad762d1d
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@ -576,7 +576,9 @@ def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad;
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// Purpose: Load Word (SP-Relative, Extended)
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// To load an SP-relative word from memory as a signed value.
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//
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def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad;
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def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
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let Uses = [SP];
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}
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//
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// Format: MOVE r32, rz MIPS16e
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@ -688,6 +690,8 @@ def RestoreRaF16:
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FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
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"restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
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let isCodeGenOnly = 1;
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let Defs = [S0, S1, RA, SP];
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let Uses = [SP];
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}
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// Use Restore to increment SP since SP is not a Mip 16 register, this
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@ -698,6 +702,8 @@ def RestoreIncSpF16:
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FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
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"restore\t$frame_size", [], IILoad >, MayLoad {
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let isCodeGenOnly = 1;
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let Defs = [SP];
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let Uses = [SP];
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}
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//
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@ -712,6 +718,8 @@ def SaveRaF16:
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FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
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"save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
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let isCodeGenOnly = 1;
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let Uses = [RA, SP, S0, S1];
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let Defs = [SP];
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}
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//
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@ -723,6 +731,8 @@ def SaveDecSpF16:
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FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
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"save\t$frame_size", [], IIStore >, MayStore {
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let isCodeGenOnly = 1;
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let Uses = [SP];
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let Defs = [SP];
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}
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//
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// Format: SB ry, offset(rx) MIPS16e
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