forked from OSchip/llvm-project
[AArch64] Fix incorrect MachinePointerInfo in splitStoreSplat
When splitting up one store into several in splitStoreSplat we have to make sure we get the MachinePointerInfo right, otherwise alias analysis thinks they all store to the same location. This can then cause invalid scheduling later on. Differential Revision: https://reviews.llvm.org/D29446 llvm-svn: 294203
This commit is contained in:
John Brawn
parent
c5f28e2a05
commit
3a9c842a9d
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@ -8923,8 +8923,9 @@ static SDValue splitStoreSplat(SelectionDAG &DAG, StoreSDNode &St,
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// instructions (stp).
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// instructions (stp).
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SDLoc DL(&St);
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SDLoc DL(&St);
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SDValue BasePtr = St.getBasePtr();
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SDValue BasePtr = St.getBasePtr();
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const MachinePointerInfo &PtrInfo = St.getPointerInfo();
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SDValue NewST1 =
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SDValue NewST1 =
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DAG.getStore(St.getChain(), DL, SplatVal, BasePtr, St.getPointerInfo(),
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DAG.getStore(St.getChain(), DL, SplatVal, BasePtr, PtrInfo,
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OrigAlignment, St.getMemOperand()->getFlags());
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OrigAlignment, St.getMemOperand()->getFlags());
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unsigned Offset = EltOffset;
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unsigned Offset = EltOffset;
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@ -8933,7 +8934,7 @@ static SDValue splitStoreSplat(SelectionDAG &DAG, StoreSDNode &St,
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SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
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SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
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DAG.getConstant(Offset, DL, MVT::i64));
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DAG.getConstant(Offset, DL, MVT::i64));
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NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
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NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
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St.getPointerInfo(), Alignment,
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PtrInfo.getWithOffset(Offset), Alignment,
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St.getMemOperand()->getFlags());
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St.getMemOperand()->getFlags());
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Offset += EltOffset;
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Offset += EltOffset;
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}
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}
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@ -0,0 +1,74 @@
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; RUN: llc -mtriple=aarch64 -mcpu=cortex-a53 < %s | FileCheck %s
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; Tests to check that zero stores which are generated as STP xzr, xzr aren't
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; scheduled incorrectly due to incorrect alias information
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
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%struct.tree_common = type { i8*, i8*, i32 }
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; Original test case which exhibited the bug
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define void @test1(%struct.tree_common* %t, i32 %code, i8* %type) {
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; CHECK-LABEL: test1:
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; CHECK: stp xzr, xzr, [x0, #8]
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; CHECK: stp xzr, x2, [x0]
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; CHECK: str w1, [x0, #16]
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entry:
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%0 = bitcast %struct.tree_common* %t to i8*
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tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 24, i32 8, i1 false)
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%code1 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 2
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store i32 %code, i32* %code1, align 8
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%type2 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 1
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store i8* %type, i8** %type2, align 8
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ret void
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}
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; Store to each struct element instead of using memset
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define void @test2(%struct.tree_common* %t, i32 %code, i8* %type) {
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; CHECK-LABEL: test2:
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; CHECK: stp xzr, xzr, [x0]
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; CHECK: str wzr, [x0, #16]
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; CHECK: str w1, [x0, #16]
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; CHECK: str x2, [x0, #8]
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entry:
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%0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 0
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%1 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 1
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%2 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 2
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store i8* zeroinitializer, i8** %0, align 8
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store i8* zeroinitializer, i8** %1, align 8
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store i32 zeroinitializer, i32* %2, align 8
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store i32 %code, i32* %2, align 8
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store i8* %type, i8** %1, align 8
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ret void
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}
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; Vector store instead of memset
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define void @test3(%struct.tree_common* %t, i32 %code, i8* %type) {
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; CHECK-LABEL: test3:
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; CHECK: stp xzr, xzr, [x0, #8]
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; CHECK: stp xzr, x2, [x0]
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; CHECK: str w1, [x0, #16]
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entry:
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%0 = bitcast %struct.tree_common* %t to <3 x i64>*
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store <3 x i64> zeroinitializer, <3 x i64>* %0, align 8
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%code1 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 2
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store i32 %code, i32* %code1, align 8
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%type2 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 1
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store i8* %type, i8** %type2, align 8
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ret void
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}
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; Vector store, then store to vector elements
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define void @test4(<3 x i64>* %p, i64 %x, i64 %y) {
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; CHECK-LABEL: test4:
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; CHECK: stp xzr, xzr, [x0, #8]
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; CHECK: stp xzr, x2, [x0]
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; CHECK: str x1, [x0, #16]
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entry:
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store <3 x i64> zeroinitializer, <3 x i64>* %p, align 8
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%0 = bitcast <3 x i64>* %p to i64*
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%1 = getelementptr inbounds i64, i64* %0, i64 2
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store i64 %x, i64* %1, align 8
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%2 = getelementptr inbounds i64, i64* %0, i64 1
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store i64 %y, i64* %2, align 8
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ret void
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}
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@ -0,0 +1,57 @@
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+use-aa -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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; Tests to check that the scheduler dependencies derived from alias analysis are
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; correct when we have loads that have been split up so that they can later be
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; merged into STP.
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; CHECK: ********** MI Scheduling **********
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; CHECK: test_splat:BB#0 entry
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; CHECK: SU({{[0-9]+}}): STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 3; mem:ST4[%3+8]
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; CHECK: Successors:
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; CHECK-NEXT: ord [[SU1:SU\([0-9]+\)]]
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; CHECK: SU({{[0-9]+}}): STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 2; mem:ST4[%3+4]
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; CHECK: Successors:
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; CHECK-NEXT: ord [[SU2:SU\([0-9]+\)]]
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; CHECK: [[SU1]]: STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 3; mem:ST4[%2]
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; CHECK: [[SU2]]: STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 2; mem:ST4[%1]
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define void @test_splat(i32 %x, i32 %y, i32* %p) {
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entry:
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%val = load i32, i32* %p, align 4
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%0 = getelementptr inbounds i32, i32* %p, i64 1
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%1 = getelementptr inbounds i32, i32* %p, i64 2
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%2 = getelementptr inbounds i32, i32* %p, i64 3
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%vec0 = insertelement <4 x i32> undef, i32 %val, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %val, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %val, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %val, i32 3
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%3 = bitcast i32* %0 to <4 x i32>*
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store <4 x i32> %vec3, <4 x i32>* %3, align 4
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store i32 %x, i32* %2, align 4
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store i32 %y, i32* %1, align 4
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ret void
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}
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
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%struct.tree_common = type { i8*, i8*, i32 }
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; CHECK: ********** MI Scheduling **********
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; CHECK: test_zero:BB#0 entry
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; CHECK: SU({{[0-9]+}}): STRXui %XZR, %vreg{{[0-9]+}}, 2; mem:ST8[%0+16]
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; CHECK: Successors:
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; CHECK-NEXT: ord [[SU3:SU\([0-9]+\)]]
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; CHECK: SU({{[0-9]+}}): STRXui %XZR, %vreg{{[0-9]+}}, 1; mem:ST8[%0+8]
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; CHECK: Successors:
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; CHECK-NEXT: ord [[SU4:SU\([0-9]+\)]]
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; CHECK: [[SU3]]: STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 4; mem:ST4[%code1]
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; CHECK: [[SU4]]: STRXui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 1; mem:ST8[%type2]
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define void @test_zero(%struct.tree_common* %t, i32 %code, i8* %type) {
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entry:
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%0 = bitcast %struct.tree_common* %t to i8*
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tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 24, i32 8, i1 false)
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%code1 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 2
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store i32 %code, i32* %code1, align 8
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%type2 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 1
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store i8* %type, i8** %type2, align 8
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ret void
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}
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