forked from OSchip/llvm-project
Annotate various null idioms with SchedRW lists.
llvm-svn: 177461
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24aac1dc92
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@ -364,7 +364,7 @@ let Predicates = [HasAVX] in {
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// Alias instructions that map fld0 to xorps for sse or vxorps for avx.
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// This is expanded by ExpandPostRAPseudos.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isPseudo = 1 in {
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isPseudo = 1, SchedRW = [WriteZero] in {
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def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
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[(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
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def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
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@ -381,7 +381,7 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-zeros value if folding it would be beneficial.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isPseudo = 1 in {
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isPseudo = 1, SchedRW = [WriteZero] in {
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def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4f32 immAllZerosV))]>;
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}
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@ -398,7 +398,7 @@ def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
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// at the rename stage without using any execution unit, so SET0PSY
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// and SET0PDY can be used for vector int instructions without penalty
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isPseudo = 1, Predicates = [HasAVX] in {
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isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
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def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
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[(set VR256:$dst, (v8f32 immAllZerosV))]>;
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}
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@ -436,7 +436,7 @@ def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-ones value if folding it would be beneficial.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isPseudo = 1 in {
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isPseudo = 1, SchedRW = [WriteZero] in {
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def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>;
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let Predicates = [HasAVX2] in
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