maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[GlobalISel][X86] Split memop test file. NFC 

llvm-svn: 303169
This commit is contained in:
Igor Breger 2017-05-16 13:37:31 +00:00
parent 8b12a03215
commit 3a45504498
6 changed files with 184 additions and 199 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
llvm/test/CodeGen/X86/GlobalISel/memop-x32.ll → llvm/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll
View File

64
llvm/test/CodeGen/X86/GlobalISel/memop.ll → llvm/test/CodeGen/X86/GlobalISel/memop-scalar.ll
View File

@ -1,13 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_FAST
; RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_GREEDY
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX_FAST
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX_GREEDY
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX512F_FAST
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX512F_GREEDY
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX512VL_FAST
; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX512VL_GREEDY
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE_FAST
; RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE_GREEDY
define i8 @test_load_i8(i8 * %p1) {
; ALL-LABEL: test_load_i8:
@ -77,34 +70,6 @@ define double @test_load_double(double * %p1) {
ret double %r
}
define <4 x i32> @test_load_v4i32_noalign(<4 x i32> * %p1) {
; SSE-LABEL: test_load_v4i32_noalign:
; SSE: # BB#0:
; SSE-NEXT: movups (%rdi), %xmm0
; SSE-NEXT: retq
;
; ALL_AVX-LABEL: test_load_v4i32_noalign:
; ALL_AVX: # BB#0:
; ALL_AVX-NEXT: vmovups (%rdi), %xmm0
; ALL_AVX-NEXT: retq
%r = load <4 x i32>, <4 x i32>* %p1, align 1
ret <4 x i32> %r
}
define <4 x i32> @test_load_v4i32_align(<4 x i32> * %p1) {
; SSE-LABEL: test_load_v4i32_align:
; SSE: # BB#0:
; SSE-NEXT: movaps (%rdi), %xmm0
; SSE-NEXT: retq
;
; ALL_AVX-LABEL: test_load_v4i32_align:
; ALL_AVX: # BB#0:
; ALL_AVX-NEXT: vmovaps (%rdi), %xmm0
; ALL_AVX-NEXT: retq
%r = load <4 x i32>, <4 x i32>* %p1, align 16
ret <4 x i32> %r
}
define i32 * @test_store_i32(i32 %val, i32 * %p1) {
; ALL-LABEL: test_store_i32:
; ALL: # BB#0:
@ -139,19 +104,6 @@ define float * @test_store_float(float %val, float * %p1) {
; SSE_GREEDY-NEXT: movss %xmm0, (%rdi)
; SSE_GREEDY-NEXT: movq %rdi, %rax
; SSE_GREEDY-NEXT: retq
;
; ALL_AVX_FAST-LABEL: test_store_float:
; ALL_AVX_FAST: # BB#0:
; ALL_AVX_FAST-NEXT: vmovd %xmm0, %eax
; ALL_AVX_FAST-NEXT: movl %eax, (%rdi)
; ALL_AVX_FAST-NEXT: movq %rdi, %rax
; ALL_AVX_FAST-NEXT: retq
;
; ALL_AVX_GREEDY-LABEL: test_store_float:
; ALL_AVX_GREEDY: # BB#0:
; ALL_AVX_GREEDY-NEXT: vmovss %xmm0, (%rdi)
; ALL_AVX_GREEDY-NEXT: movq %rdi, %rax
; ALL_AVX_GREEDY-NEXT: retq
store float %val, float* %p1
ret float * %p1;
}
@ -171,18 +123,6 @@ define double * @test_store_double(double %val, double * %p1) {
; SSE_GREEDY-NEXT: movq %rdi, %rax
; SSE_GREEDY-NEXT: retq
;
; ALL_AVX_FAST-LABEL: test_store_double:
; ALL_AVX_FAST: # BB#0:
; ALL_AVX_FAST-NEXT: vmovq %xmm0, %rax
; ALL_AVX_FAST-NEXT: movq %rax, (%rdi)
; ALL_AVX_FAST-NEXT: movq %rdi, %rax
; ALL_AVX_FAST-NEXT: retq
;
; ALL_AVX_GREEDY-LABEL: test_store_double:
; ALL_AVX_GREEDY: # BB#0:
; ALL_AVX_GREEDY-NEXT: vmovsd %xmm0, (%rdi)
; ALL_AVX_GREEDY-NEXT: movq %rdi, %rax
; ALL_AVX_GREEDY-NEXT: retq
store double %val, double* %p1
ret double * %p1;
}

39
llvm/test/CodeGen/X86/GlobalISel/memop-vec.ll Normal file
View File

@ -0,0 +1,39 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SKX
; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SKX
define <4 x i32> @test_load_v4i32_noalign(<4 x i32> * %p1) {
; ALL-LABEL: test_load_v4i32_noalign:
; ALL: # BB#0:
; ALL-NEXT: vmovups (%rdi), %xmm0
; ALL-NEXT: retq
%r = load <4 x i32>, <4 x i32>* %p1, align 1
ret <4 x i32> %r
}
define <4 x i32> @test_load_v4i32_align(<4 x i32> * %p1) {
; ALL-LABEL: test_load_v4i32_align:
; ALL: # BB#0:
; ALL-NEXT: vmovaps (%rdi), %xmm0
; ALL-NEXT: retq
%r = load <4 x i32>, <4 x i32>* %p1, align 16
ret <4 x i32> %r
}
define void @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) {
; ALL-LABEL: test_store_v4i32_noalign:
; ALL: # BB#0:
; ALL-NEXT: vmovups %xmm0, (%rdi)
; ALL-NEXT: retq
store <4 x i32> %val, <4 x i32>* %p1, align 1
ret void
}
define void @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) {
; ALL-LABEL: test_store_v4i32_align:
; ALL: # BB#0:
; ALL-NEXT: vmovaps %xmm0, (%rdi)
; ALL-NEXT: retq
store <4 x i32> %val, <4 x i32>* %p1, align 16
ret void
}

0
llvm/test/CodeGen/X86/GlobalISel/select-memop-x32.mir → llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
View File

137
llvm/test/CodeGen/X86/GlobalISel/select-memop.mir → llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
View File

@ -34,7 +34,6 @@
ret float %r
}
define double @test_load_double(double* %p1) {
%r = load double, double* %p1
ret double %r
@ -45,16 +44,6 @@
ret double %r
}
define <4 x i32> @test_load_v4i32_noalign(<4 x i32>* %p1) {
%r = load <4 x i32>, <4 x i32>* %p1, align 1
ret <4 x i32> %r
}
define <4 x i32> @test_load_v4i32_align(<4 x i32>* %p1) {
%r = load <4 x i32>, <4 x i32>* %p1, align 16
ret <4 x i32> %r
}
define i32* @test_store_i32(i32 %val, i32* %p1) {
store i32 %val, i32* %p1
ret i32* %p1
@ -85,16 +74,6 @@
ret double* %p1
}
define <4 x i32>* @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) {
store <4 x i32> %val, <4 x i32>* %p1, align 16
ret <4 x i32>* %p1
}
define <4 x i32>* @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) {
store <4 x i32> %val, <4 x i32>* %p1, align 1
ret <4 x i32>* %p1
}
define i32* @test_load_ptr(i32** %ptr1) {
%p = load i32*, i32** %ptr1
ret i32* %p
@ -302,62 +281,6 @@ body: |
%xmm0 = COPY %1(s64)
RET 0, implicit %xmm0
...
---
# ALL-LABEL: name: test_load_v4i32_noalign
name: test_load_v4i32_noalign
alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# NO_AVX512F: - { id: 1, class: vr128 }
# AVX512ALL: - { id: 1, class: vr128x }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
# ALL: %0 = COPY %rdi
# SSE: %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
# AVX: %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
# AVX512F: %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
# AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
liveins: %rdi
%0(p0) = COPY %rdi
%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
%xmm0 = COPY %1(<4 x s32>)
RET 0, implicit %xmm0
...
---
# ALL-LABEL: name: test_load_v4i32_align
name: test_load_v4i32_align
alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# NO_AVX512F: - { id: 1, class: vr128 }
# AVX512ALL: - { id: 1, class: vr128x }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
# ALL: %0 = COPY %rdi
# SSE: %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
# AVX: %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
# AVX512F: %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
# AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
liveins: %rdi
%0(p0) = COPY %rdi
%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1)
%xmm0 = COPY %1(<4 x s32>)
RET 0, implicit %xmm0
...
---
# ALL-LABEL: name: test_store_i32
@ -528,66 +451,6 @@ body: |
%rax = COPY %1(p0)
RET 0, implicit %rax
...
---
# ALL-LABEL: name: test_store_v4i32_align
name: test_store_v4i32_align
alignment: 4
legalized: true
regBankSelected: true
registers:
# NO_AVX512F: - { id: 0, class: vr128 }
# AVX512ALL: - { id: 0, class: vr128x }
# ALL: - { id: 1, class: gr64 }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %xmm0
# ALL: %1 = COPY %rdi
# SSE: MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# AVX: VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# AVX512VL: VMOVAPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# ALL: %rax = COPY %1
body: |
bb.1 (%ir-block.0):
liveins: %rdi, %xmm0
%0(<4 x s32>) = COPY %xmm0
%1(p0) = COPY %rdi
G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 16)
%rax = COPY %1(p0)
RET 0, implicit %rax
...
---
# ALL-LABEL: name: test_store_v4i32_noalign
name: test_store_v4i32_noalign
alignment: 4
legalized: true
regBankSelected: true
registers:
# NO_AVX512F: - { id: 0, class: vr128 }
# AVX512ALL: - { id: 0, class: vr128x }
# ALL: - { id: 1, class: gr64 }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %xmm0
# ALL: %1 = COPY %rdi
# SSE: MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# AVX: VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# AVX512VL: VMOVUPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# ALL: %rax = COPY %1
body: |
bb.1 (%ir-block.0):
liveins: %rdi, %xmm0
%0(<4 x s32>) = COPY %xmm0
%1(p0) = COPY %rdi
G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 1)
%rax = COPY %1(p0)
RET 0, implicit %rax
...
---
# ALL-LABEL: name: test_load_ptr

143
llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir Normal file
View File

@ -0,0 +1,143 @@
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
--- |
define <4 x i32> @test_load_v4i32_noalign(<4 x i32>* %p1) {
%r = load <4 x i32>, <4 x i32>* %p1, align 1
ret <4 x i32> %r
}
define <4 x i32> @test_load_v4i32_align(<4 x i32>* %p1) {
%r = load <4 x i32>, <4 x i32>* %p1, align 16
ret <4 x i32> %r
}
define <4 x i32>* @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) {
store <4 x i32> %val, <4 x i32>* %p1, align 16
ret <4 x i32>* %p1
}
define <4 x i32>* @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) {
store <4 x i32> %val, <4 x i32>* %p1, align 1
ret <4 x i32>* %p1
}
...
---
# ALL-LABEL: name: test_load_v4i32_noalign
name: test_load_v4i32_noalign
alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# NO_AVX512F: - { id: 1, class: vr128 }
# AVX512ALL: - { id: 1, class: vr128x }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
# ALL: %0 = COPY %rdi
# SSE: %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
# AVX: %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
# AVX512F: %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
# AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
liveins: %rdi
%0(p0) = COPY %rdi
%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
%xmm0 = COPY %1(<4 x s32>)
RET 0, implicit %xmm0
...
---
# ALL-LABEL: name: test_load_v4i32_align
name: test_load_v4i32_align
alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# NO_AVX512F: - { id: 1, class: vr128 }
# AVX512ALL: - { id: 1, class: vr128x }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
# ALL: %0 = COPY %rdi
# SSE: %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
# AVX: %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
# AVX512F: %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
# AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
liveins: %rdi
%0(p0) = COPY %rdi
%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1)
%xmm0 = COPY %1(<4 x s32>)
RET 0, implicit %xmm0
...
---
# ALL-LABEL: name: test_store_v4i32_align
name: test_store_v4i32_align
alignment: 4
legalized: true
regBankSelected: true
registers:
# NO_AVX512F: - { id: 0, class: vr128 }
# AVX512ALL: - { id: 0, class: vr128x }
# ALL: - { id: 1, class: gr64 }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %xmm0
# ALL: %1 = COPY %rdi
# SSE: MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# AVX: VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# AVX512VL: VMOVAPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# ALL: %rax = COPY %1
body: |
bb.1 (%ir-block.0):
liveins: %rdi, %xmm0
%0(<4 x s32>) = COPY %xmm0
%1(p0) = COPY %rdi
G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 16)
%rax = COPY %1(p0)
RET 0, implicit %rax
...
---
# ALL-LABEL: name: test_store_v4i32_noalign
name: test_store_v4i32_noalign
alignment: 4
legalized: true
regBankSelected: true
registers:
# NO_AVX512F: - { id: 0, class: vr128 }
# AVX512ALL: - { id: 0, class: vr128x }
# ALL: - { id: 1, class: gr64 }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %xmm0
# ALL: %1 = COPY %rdi
# SSE: MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# AVX: VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# AVX512VL: VMOVUPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# ALL: %rax = COPY %1
body: |
bb.1 (%ir-block.0):
liveins: %rdi, %xmm0
%0(<4 x s32>) = COPY %xmm0
%1(p0) = COPY %rdi
G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 1)
%rax = COPY %1(p0)
RET 0, implicit %rax
...