From 3a45369b9eab62233c2f13f31eb14d7ea7445e12 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 18 Jul 2018 13:01:20 +0000 Subject: [PATCH] [X86][SSE] Remove BLENDPD canonicalization from combineTargetShuffle When rL336971 removed the scalar-fp isel patterns, we lost the need for this canonicalization - commutation/folding can handle everything else. llvm-svn: 337387 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 7a32ce59d314..37252de7dbc7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -30696,31 +30696,6 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG, } return SDValue(); } - case X86ISD::BLENDI: { - SDValue V0 = N->getOperand(0); - SDValue V1 = N->getOperand(1); - assert(VT == V0.getSimpleValueType() && VT == V1.getSimpleValueType() && - "Unexpected input vector types"); - - // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector - // operands and changing the mask to 1. This saves us a bunch of - // pattern-matching possibilities related to scalar math ops in SSE/AVX. - // x86InstrInfo knows how to commute this back after instruction selection - // if it would help register allocation. - - // TODO: If optimizing for size or a processor that doesn't suffer from - // partial register update stalls, this should be transformed into a MOVSD - // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD. - - if (VT == MVT::v2f64) - if (auto *Mask = dyn_cast(N->getOperand(2))) - if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) { - SDValue NewMask = DAG.getConstant(1, DL, MVT::i8); - return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask); - } - - return SDValue(); - } case X86ISD::MOVSD: case X86ISD::MOVSS: { SDValue V0 = peekThroughBitcasts(N->getOperand(0));