forked from OSchip/llvm-project
Add support for some of the LLVM atomic operations to the MBlaze backend.
llvm-svn: 122384
This commit is contained in:
Wesley Peck
parent
77c4697735
commit
3a3a5795c5
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@ -175,7 +175,6 @@ MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
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// Use the default for now
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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// MBlaze doesn't have extending float->double load/store
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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@ -213,172 +212,353 @@ SDValue MBlazeTargetLowering::LowerOperation(SDValue Op,
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//===----------------------------------------------------------------------===//
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MachineBasicBlock*
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MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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MachineBasicBlock *MBB)
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const {
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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case MBlaze::ShiftRL:
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case MBlaze::ShiftRA:
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case MBlaze::ShiftL:
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return EmitCustomShift(MI, MBB);
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case MBlaze::Select_FCC:
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case MBlaze::Select_CC:
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return EmitCustomSelect(MI, MBB);
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case MBlaze::CAS32:
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case MBlaze::SWP32:
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case MBlaze::LAA32:
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case MBlaze::LAS32:
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case MBlaze::LAD32:
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case MBlaze::LAO32:
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case MBlaze::LAX32:
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case MBlaze::LAN32:
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return EmitCustomAtomic(MI, MBB);
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case MBlaze::MEMBARRIER:
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// The Microblaze does not need memory barriers. Just delete the pseudo
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// instruction and finish.
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MI->eraseFromParent();
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return MBB;
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}
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}
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MachineBasicBlock*
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MBlazeTargetLowering::EmitCustomShift(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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// To "insert" a shift left instruction, we actually have to insert a
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// simple loop. The incoming instruction knows the destination vreg to
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// set, the source vreg to operate over and the shift amount.
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const BasicBlock *LLVM_BB = MBB->getBasicBlock();
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MachineFunction::iterator It = MBB;
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++It;
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// start:
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// andi samt, samt, 31
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// beqid samt, finish
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// add dst, src, r0
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// loop:
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// addik samt, samt, -1
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// sra dst, dst
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// bneid samt, loop
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// nop
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// finish:
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MachineFunction *F = MBB->getParent();
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MachineRegisterInfo &R = F->getRegInfo();
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MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, loop);
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F->insert(It, finish);
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// Update machine-CFG edges by transfering adding all successors and
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// remaining instructions from the current block to the new block which
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// will contain the Phi node for the select.
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finish->splice(finish->begin(), MBB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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MBB->end());
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finish->transferSuccessorsAndUpdatePHIs(MBB);
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// Add the true and fallthrough blocks as its successors.
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MBB->addSuccessor(loop);
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MBB->addSuccessor(finish);
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// Next, add the finish block as a successor of the loop block
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loop->addSuccessor(finish);
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loop->addSuccessor(loop);
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unsigned IAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT)
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.addReg(MI->getOperand(2).getReg())
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.addImm(31);
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unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL)
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.addReg(MI->getOperand(1).getReg())
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.addImm(0);
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BuildMI(MBB, dl, TII->get(MBlaze::BEQID))
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.addReg(IAMT)
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.addMBB(finish);
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unsigned DST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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unsigned NDST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
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.addReg(IVAL).addMBB(MBB)
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.addReg(NDST).addMBB(loop);
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unsigned SAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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unsigned NAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
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.addReg(IAMT).addMBB(MBB)
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.addReg(NAMT).addMBB(loop);
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if (MI->getOpcode() == MBlaze::ShiftL)
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BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
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else if (MI->getOpcode() == MBlaze::ShiftRA)
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BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
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else if (MI->getOpcode() == MBlaze::ShiftRL)
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BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
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else
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llvm_unreachable("Cannot lower unknown shift instruction");
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BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
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.addReg(SAMT)
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.addImm(-1);
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BuildMI(loop, dl, TII->get(MBlaze::BNEID))
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.addReg(NAMT)
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.addMBB(loop);
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BuildMI(*finish, finish->begin(), dl,
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TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
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.addReg(IVAL).addMBB(MBB)
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.addReg(NDST).addMBB(loop);
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// The pseudo instruction is no longer needed so remove it
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MI->eraseFromParent();
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return finish;
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}
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MachineBasicBlock*
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MBlazeTargetLowering::EmitCustomSelect(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = MBB->getBasicBlock();
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MachineFunction::iterator It = MBB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// setcc r1, r2, r3
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// bNE r1, r0, copy1MBB
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// fallthrough --> copy0MBB
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MachineFunction *F = MBB->getParent();
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MachineBasicBlock *flsBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *dneBB = F->CreateMachineBasicBlock(LLVM_BB);
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unsigned Opc;
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switch (MI->getOperand(4).getImm()) {
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default: llvm_unreachable("Unknown branch condition");
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case MBlazeCC::EQ: Opc = MBlaze::BEQID; break;
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case MBlazeCC::NE: Opc = MBlaze::BNEID; break;
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case MBlazeCC::GT: Opc = MBlaze::BGTID; break;
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case MBlazeCC::LT: Opc = MBlaze::BLTID; break;
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case MBlazeCC::GE: Opc = MBlaze::BGEID; break;
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case MBlazeCC::LE: Opc = MBlaze::BLEID; break;
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}
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F->insert(It, flsBB);
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F->insert(It, dneBB);
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// Transfer the remainder of MBB and its successor edges to dneBB.
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dneBB->splice(dneBB->begin(), MBB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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MBB->end());
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dneBB->transferSuccessorsAndUpdatePHIs(MBB);
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MBB->addSuccessor(flsBB);
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MBB->addSuccessor(dneBB);
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flsBB->addSuccessor(dneBB);
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BuildMI(MBB, dl, TII->get(Opc))
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.addReg(MI->getOperand(3).getReg())
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.addMBB(dneBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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//BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
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// .addReg(MI->getOperand(1).getReg()).addMBB(flsBB)
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// .addReg(MI->getOperand(2).getReg()).addMBB(BB);
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BuildMI(*dneBB, dneBB->begin(), dl,
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TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg()).addMBB(flsBB)
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.addReg(MI->getOperand(1).getReg()).addMBB(MBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return dneBB;
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}
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MachineBasicBlock*
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MBlazeTargetLowering::EmitCustomAtomic(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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// All atomic instructions on the Microblaze are implemented using the
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// load-linked / store-conditional style atomic instruction sequences.
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// Thus, all operations will look something like the following:
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//
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// start:
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// lwx RV, RP, 0
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// <do stuff>
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// swx RV, RP, 0
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// addic RC, R0, 0
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// bneid RC, start
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//
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// exit:
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//
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// To "insert" a shift left instruction, we actually have to insert a
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// simple loop. The incoming instruction knows the destination vreg to
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// set, the source vreg to operate over and the shift amount.
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const BasicBlock *LLVM_BB = MBB->getBasicBlock();
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MachineFunction::iterator It = MBB;
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++It;
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// start:
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// andi samt, samt, 31
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// beqid samt, finish
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// add dst, src, r0
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// loop:
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// addik samt, samt, -1
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// sra dst, dst
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// bneid samt, loop
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// nop
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// finish:
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MachineFunction *F = MBB->getParent();
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MachineRegisterInfo &R = F->getRegInfo();
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// Create the start and exit basic blocks for the atomic operation
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MachineBasicBlock *start = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exit = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, start);
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F->insert(It, exit);
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// Update machine-CFG edges by transfering adding all successors and
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// remaining instructions from the current block to the new block which
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// will contain the Phi node for the select.
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exit->splice(exit->begin(), MBB, llvm::next(MachineBasicBlock::iterator(MI)),
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MBB->end());
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exit->transferSuccessorsAndUpdatePHIs(MBB);
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// Add the fallthrough block as its successors.
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MBB->addSuccessor(start);
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BuildMI(start, dl, TII->get(MBlaze::LWX), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addReg(MBlaze::R0);
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MachineBasicBlock *final = start;
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unsigned finalReg = 0;
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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case MBlaze::ShiftRL:
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case MBlaze::ShiftRA:
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case MBlaze::ShiftL: {
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// To "insert" a shift left instruction, we actually have to insert a
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// simple loop. The incoming instruction knows the destination vreg to
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// set, the source vreg to operate over and the shift amount.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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default: llvm_unreachable("Cannot lower unknown atomic instruction!");
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// start:
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// andi samt, samt, 31
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// beqid samt, finish
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// add dst, src, r0
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// loop:
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// addik samt, samt, -1
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// sra dst, dst
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// bneid samt, loop
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// nop
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// finish:
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MachineFunction *F = BB->getParent();
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MachineRegisterInfo &R = F->getRegInfo();
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MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, loop);
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F->insert(It, finish);
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case MBlaze::SWP32:
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finalReg = MI->getOperand(2).getReg();
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start->addSuccessor(exit);
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start->addSuccessor(start);
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break;
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// Update machine-CFG edges by transfering adding all successors and
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// remaining instructions from the current block to the new block which
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// will contain the Phi node for the select.
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finish->splice(finish->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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finish->transferSuccessorsAndUpdatePHIs(BB);
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// Add the true and fallthrough blocks as its successors.
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BB->addSuccessor(loop);
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BB->addSuccessor(finish);
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// Next, add the finish block as a successor of the loop block
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loop->addSuccessor(finish);
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loop->addSuccessor(loop);
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unsigned IAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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BuildMI(BB, dl, TII->get(MBlaze::ANDI), IAMT)
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.addReg(MI->getOperand(2).getReg())
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.addImm(31);
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unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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BuildMI(BB, dl, TII->get(MBlaze::ADDIK), IVAL)
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.addReg(MI->getOperand(1).getReg())
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.addImm(0);
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BuildMI(BB, dl, TII->get(MBlaze::BEQID))
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.addReg(IAMT)
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.addMBB(finish);
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unsigned DST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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unsigned NDST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
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.addReg(IVAL).addMBB(BB)
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.addReg(NDST).addMBB(loop);
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unsigned SAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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unsigned NAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
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.addReg(IAMT).addMBB(BB)
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.addReg(NAMT).addMBB(loop);
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if (MI->getOpcode() == MBlaze::ShiftL)
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BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
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else if (MI->getOpcode() == MBlaze::ShiftRA)
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BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
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else if (MI->getOpcode() == MBlaze::ShiftRL)
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BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
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else
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llvm_unreachable("Cannot lower unknown shift instruction");
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BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
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.addReg(SAMT)
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.addImm(-1);
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BuildMI(loop, dl, TII->get(MBlaze::BNEID))
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.addReg(NAMT)
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.addMBB(loop);
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BuildMI(*finish, finish->begin(), dl,
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TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
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.addReg(IVAL).addMBB(BB)
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.addReg(NDST).addMBB(loop);
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// The pseudo instruction is no longer needed so remove it
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MI->eraseFromParent();
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return finish;
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case MBlaze::LAN32:
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case MBlaze::LAX32:
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case MBlaze::LAO32:
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case MBlaze::LAD32:
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case MBlaze::LAS32:
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case MBlaze::LAA32: {
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unsigned opcode = 0;
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switch (MI->getOpcode()) {
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default: llvm_unreachable("Cannot lower unknown atomic load!");
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case MBlaze::LAA32: opcode = MBlaze::ADDIK; break;
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case MBlaze::LAS32: opcode = MBlaze::RSUBIK; break;
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case MBlaze::LAD32: opcode = MBlaze::AND; break;
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case MBlaze::LAO32: opcode = MBlaze::OR; break;
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case MBlaze::LAX32: opcode = MBlaze::XOR; break;
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case MBlaze::LAN32: opcode = MBlaze::AND; break;
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}
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case MBlaze::Select_FCC:
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case MBlaze::Select_CC: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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finalReg = R.createVirtualRegister(MBlaze::GPRRegisterClass);
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start->addSuccessor(exit);
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start->addSuccessor(start);
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// thisMBB:
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// ...
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// TrueVal = ...
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// setcc r1, r2, r3
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// bNE r1, r0, copy1MBB
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// fallthrough --> copy0MBB
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *flsBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *dneBB = F->CreateMachineBasicBlock(LLVM_BB);
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BuildMI(start, dl, TII->get(opcode), finalReg)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg());
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unsigned Opc;
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switch (MI->getOperand(4).getImm()) {
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default: llvm_unreachable("Unknown branch condition");
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case MBlazeCC::EQ: Opc = MBlaze::BEQID; break;
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case MBlazeCC::NE: Opc = MBlaze::BNEID; break;
|
||||
case MBlazeCC::GT: Opc = MBlaze::BGTID; break;
|
||||
case MBlazeCC::LT: Opc = MBlaze::BLTID; break;
|
||||
case MBlazeCC::GE: Opc = MBlaze::BGEID; break;
|
||||
case MBlazeCC::LE: Opc = MBlaze::BLEID; break;
|
||||
if (MI->getOpcode() == MBlaze::LAN32) {
|
||||
unsigned tmp = finalReg;
|
||||
finalReg = R.createVirtualRegister(MBlaze::GPRRegisterClass);
|
||||
BuildMI(start, dl, TII->get(MBlaze::XORI), finalReg)
|
||||
.addReg(tmp)
|
||||
.addImm(-1);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
F->insert(It, flsBB);
|
||||
F->insert(It, dneBB);
|
||||
case MBlaze::CAS32: {
|
||||
finalReg = MI->getOperand(3).getReg();
|
||||
final = F->CreateMachineBasicBlock(LLVM_BB);
|
||||
|
||||
// Transfer the remainder of BB and its successor edges to dneBB.
|
||||
dneBB->splice(dneBB->begin(), BB,
|
||||
llvm::next(MachineBasicBlock::iterator(MI)),
|
||||
BB->end());
|
||||
dneBB->transferSuccessorsAndUpdatePHIs(BB);
|
||||
F->insert(It, final);
|
||||
start->addSuccessor(exit);
|
||||
start->addSuccessor(final);
|
||||
final->addSuccessor(exit);
|
||||
final->addSuccessor(start);
|
||||
|
||||
BB->addSuccessor(flsBB);
|
||||
BB->addSuccessor(dneBB);
|
||||
flsBB->addSuccessor(dneBB);
|
||||
unsigned CMP = R.createVirtualRegister(MBlaze::GPRRegisterClass);
|
||||
BuildMI(start, dl, TII->get(MBlaze::CMP), CMP)
|
||||
.addReg(MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(2).getReg());
|
||||
|
||||
BuildMI(BB, dl, TII->get(Opc))
|
||||
.addReg(MI->getOperand(3).getReg())
|
||||
.addMBB(dneBB);
|
||||
BuildMI(start, dl, TII->get(MBlaze::BNEID))
|
||||
.addReg(CMP)
|
||||
.addMBB(exit);
|
||||
|
||||
// sinkMBB:
|
||||
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
||||
// ...
|
||||
//BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
|
||||
// .addReg(MI->getOperand(1).getReg()).addMBB(flsBB)
|
||||
// .addReg(MI->getOperand(2).getReg()).addMBB(BB);
|
||||
|
||||
BuildMI(*dneBB, dneBB->begin(), dl,
|
||||
TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(2).getReg()).addMBB(flsBB)
|
||||
.addReg(MI->getOperand(1).getReg()).addMBB(BB);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
return dneBB;
|
||||
final->moveAfter(start);
|
||||
exit->moveAfter(final);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned CHK = R.createVirtualRegister(MBlaze::GPRRegisterClass);
|
||||
BuildMI(final, dl, TII->get(MBlaze::SWX))
|
||||
.addReg(finalReg)
|
||||
.addReg(MI->getOperand(1).getReg())
|
||||
.addReg(MBlaze::R0);
|
||||
|
||||
BuildMI(final, dl, TII->get(MBlaze::ADDIC), CHK)
|
||||
.addReg(MBlaze::R0)
|
||||
.addImm(0);
|
||||
|
||||
BuildMI(final, dl, TII->get(MBlaze::BNEID))
|
||||
.addReg(CHK)
|
||||
.addMBB(start);
|
||||
|
||||
// The pseudo instruction is no longer needed so remove it
|
||||
MI->eraseFromParent();
|
||||
return exit;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -149,6 +149,15 @@ namespace llvm {
|
|||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
DebugLoc dl, SelectionDAG &DAG) const;
|
||||
|
||||
virtual MachineBasicBlock*
|
||||
EmitCustomShift(MachineInstr *MI, MachineBasicBlock *MBB) const;
|
||||
|
||||
virtual MachineBasicBlock*
|
||||
EmitCustomSelect(MachineInstr *MI, MachineBasicBlock *MBB) const;
|
||||
|
||||
virtual MachineBasicBlock*
|
||||
EmitCustomAtomic(MachineInstr *MI, MachineBasicBlock *MBB) const;
|
||||
|
||||
virtual MachineBasicBlock *
|
||||
EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
MachineBasicBlock *MBB) const;
|
||||
|
|
|
|||
|
|
@ -668,6 +668,47 @@ def BRKI : BranchLI<0x2E, 0x0C, "brki ">;
|
|||
def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm),
|
||||
"imm $imm", [], IIAlu>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Pseudo instructions for atomic operations
|
||||
//===----------------------------------------------------------------------===//
|
||||
let usesCustomInserter=1 in {
|
||||
def CAS32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$cmp, GPR:$swp),
|
||||
"# atomic compare and swap",
|
||||
[(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$cmp, GPR:$swp))]>;
|
||||
|
||||
def SWP32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$swp),
|
||||
"# atomic swap",
|
||||
[(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$swp))]>;
|
||||
|
||||
def LAA32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val),
|
||||
"# atomic load and add",
|
||||
[(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$val))]>;
|
||||
|
||||
def LAS32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val),
|
||||
"# atomic load and sub",
|
||||
[(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$val))]>;
|
||||
|
||||
def LAD32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val),
|
||||
"# atomic load and and",
|
||||
[(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$val))]>;
|
||||
|
||||
def LAO32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val),
|
||||
"# atomic load and or",
|
||||
[(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$val))]>;
|
||||
|
||||
def LAX32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val),
|
||||
"# atomic load and xor",
|
||||
[(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$val))]>;
|
||||
|
||||
def LAN32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val),
|
||||
"# atomic load and nand",
|
||||
[(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$val))]>;
|
||||
|
||||
def MEMBARRIER : MBlazePseudo<(outs), (ins),
|
||||
"# memory barrier",
|
||||
[(membarrier (i32 imm), (i32 imm), (i32 imm), (i32 imm), (i32 imm))]>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Arbitrary patterns that map to one or more instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
Loading…
Reference in New Issue